Semiconductor device with metal extrusion formation

Patent metadata

Field	Value
Publication number	US-2016343798-A1
Application number	US-201615226186-A
Country	US
Kind code	A1
Filing date	Aug 2, 2016
Priority date	Jun 25, 2014
Publication date	Nov 24, 2016
Grant date	—

Abstract

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

First claim

What is claimed:

1 . A semiconductor structure comprising:
a Metal-insulator-metal (MIM) capacitor formed on a substrate, having a top plate, a bottom plate, and a dielectric layer; wherein: the bottom plate includes a first conductor formed on the substrate; the dielectric layer includes an insulating layer formed on the first conductor; the top plate includes a second conductor formed on the dielectric layer; and the first conductor having an exposed portion of a top surface and an exposed portion of a side surface during an annealing process.

2 . The semiconductor structure of claim 1 , wherein the first conductor further comprises:
subsequent to the annealing process, the exposed portion of the side surface includes a substantially extrusion-free side surface.

3 . The semiconductor structure of claim 1 , wherein the first conductor further compnses:
subsequent to the annealing process, the exposed portion of the top surface includes one or more extrusions in the top surface of the first conductor.

4 . The semiconductor structure of claim 1 , wherein the first conductor having the exposed portion of the top surface further comprises:
a portion of the first conductor with the dielectric layer and the top plate removed.

5 . The semiconductor structure of claim 1 , wherein the first conductor comprises at least one layer comprising one or more of: Cu, Al, Al doped with Cu, W, Ti, and TiN.

6 . The semiconductor structure of claim 1 , wherein the dielectric layer comprises at least one of: SiC, Si 3 N 4 , Si02, and a low-K dielectric.

7 . The semiconductor structure of claim 1 , wherein the first conductor includes a layer of TiAh subsequent to the annealing process.

8 . A semiconductor structure for an annealed metal wire comprising:
a semiconductor device formed on a substrate, having a conductor, and a dielectric layer; wherein: the conductor formed on the substrate; the dielectric layer includes an insulating layer formed on the conductor; the conductor having an exposed portion of a top surface and an exposed portion of a side surface during an annealing process.

9 . The semiconductor structure of claim 8 , further comprising:
subsequent to the annealing process, the exposed portion of the side surface includes a substantially extrusion-free side surface, and the exposed portion of the top surface includes one or more extrusions in the top surface of the conductor.

Assignees

• IBM

Inventors

• Levy Max G
• Milo Gary L
• Thomas David C

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title