CMOS Structures and Processes Based on Selective Thinning

Patent metadata

Field	Value
Publication number	US-2016307907-A1
Application number	US-201615172814-A
Country	US
Kind code	A1
Filing date	Jun 3, 2016
Priority date	Aug 23, 2011
Publication date	Oct 20, 2016
Grant date	—

Abstract

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

First claim

1 - 20 . (canceled)

21 . A semiconductor chip, comprising:
a substrate having a semiconducting surface comprising a first layer formed directly on a second layer, the semiconducting surface having formed therein a plurality of active regions extending through the first layer and the second layer, the plurality of active regions comprising at least a first active region and a second active region, the first layer comprising a substantially undoped layer, and the second layer comprising a highly doped screening layer; and first and second transistors formed in each of the first active region and the second active region, each of the transistors having a first and second gate insulators, respectively, wherein a thickness of the first layer in the first active region is thinner than a thickness of the first layer in the second active region, and a thickness of the first gate insulator is thinner than a thickness of the second gate insulator.

22 . The semiconductor chip of claim 1 , wherein a thickness of the second layer in the first active region and a thickness of the second layer in the second active region are substantially the same, and wherein a position of a boundary between the first layer and the second layer for each of the first active region and the second active region is substantially the same throughout the substrate.

23 . The semiconductor chip of claim 1 , wherein the first layer in the first active region and the first layer in the second active region are each an undoped single epitaxial layer of a single semiconductor material.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Hoffmann Thomas
• Scudder Lance
• Sridharan Urupattur C
• Zhao Dalong
• Ranade Pushkar
• Duane Michael
• Gregory Paul

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0167 Primary

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title