Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016268304-A1
Application number	US-201615067830-A
Country	US
Kind code	A1
Filing date	Mar 11, 2016
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

First claim

What is claimed is:

1 . A nonvolatile semiconductor memory device, comprising:
a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit, the memory cell array comprising a plurality of first conductive layers, the plurality of first conductive layers being connected to the memory cells and arranged in a stacking direction, and the wiring line portion comprising: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode layer disposed on a surface of the channel semiconductor layer via a gate insulating film.

2 . The memory device according to claim 1 , wherein
one gate electrode layer is shared by a plurality of the channel semiconductor layers.

3 . The memory device according to claim 1 , wherein
the channel semiconductor layer is provided along a second direction crossing the stacking direction and the first direction.

4 . The memory device according to claim 3 , wherein
one gate electrode layer is shared by a plurality of the channel semiconductor layers.

5 . The memory device according to claim 4 , wherein
the gate electrode layer is provided with a zigzag shape.

6 . The memory device according to claim 4 , wherein the gate electrode layer has a first gate electrode layer and a second gate electrode layer, the first gate electrode layer being provided above a first surface of the channel semiconductor layer via a gate insulating film, the second electrode layer being provided above a second surface of the channel semiconductor layer opposite to the first surface, via a gate insulating film.

7 . The memory device according to claim 1 , wherein
the channel semiconductor layer is configured by an oxide semiconductor.

8 . The memory device according to claim 1 , wherein
the channel semiconductor layer is configured by polysilicon or an oxide semiconductor.

9 . The memory device according to claim 8 , wherein
one gate electrode layer is shared by a plurality of the channel semiconductor layers.

10 . The memory device according to claim 8 , wherein
the channel semiconductor layer is provided along a second direction crossing the stacking direction and the first direction.

11 . The memory device according to claim 1 , wherein
the memory cell array further comprises: a semiconductor layer extending in a direction crossing a surface of the substrate; and a memory gate insulating film disposed so as to cover a side surface of the semiconductor layer, the memory gate insulating film, and the plurality of first conductive layers are disposed so as to cover the memory gate insulating film.

12 . The memory device according to claim 1 , wherein
the wiring line portion further comprises a capacitor or resistance element disposed above the second conductive layer.

13 . The memory device according to claim 12 , wherein the capacitor or the resistance element comprises a first semiconductor layer, and a first electrode layer disposed on a surface of the first semiconductor layer via a first insulating film.

14 . The memory device according to claim 13 , wherein
the first semiconductor layer, the first electrode layer and the first insulating film are formed of the same materials as those of the channel semiconductor layer, the gate electrode layer and the gate insulating film.

15 . A nonvolatile semiconductor memory device, comprising:
a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit, the memory cell array comprising a plurality of first conductive layers, the plurality of first conductive layers being connected to the memory cells and arranged in a stacking direction, and the wiring line portion comprising: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; and a capacitor or resistance element disposed above the second conductive layer.

16 . The memory device according to claim 15 , wherein the capacitor or the resistance element comprises a first semiconductor layer, and a first electrode layer disposed on a surface of the first semiconductor layer via a first insulating film.

Assignees

• Toshiba Kk

Inventors

• Ikeda Keiji
• Saitoh Masumi
• Aochi Hideaki
• Kamigaichi Takeshi
• Fujiki Jun

Classifications

• H01L29/24

  Electricity · mapped topic

• H01L28/20

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic