Semiconductor device

US8969867B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8969867-B2
Application numberUS-201313738443-A
CountryUS
Kind codeB2
Filing dateJan 10, 2013
Priority dateJan 18, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10 −5 Ω·m or more and 4.8×10 −3 Ω·m or less.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: an oxide semiconductor film including a first region, a second region, and a channel formation region between the first region and the second region; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film; a gate electrode layer overlapping with the channel formation region; and a gate insulating film between the oxide semiconductor film and the gate electrode layer…

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What does patent US8969867B2 cover?
The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtain…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).