Nonvolatile semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9786683-B1
Application number	US-201615271407-A
Country	US
Kind code	B1
Filing date	Sep 21, 2016
Priority date	Mar 18, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including a memory cell;
a wiring part connecting the memory cell array to an external circuit; and
a transistor that connects the wiring part and the external circuit,
the transistor comprising:
a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region;
a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and
a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

2. The memory device according to claim 1 , further comprising
a second insulating layer disposed on the first region via the semiconductor layer.

3. The memory device according to claim 2 , wherein
the first insulating layer includes a plurality of the first regions whose upper surfaces are in a lower position than that of the second region is, on at least one side of the second region, and the third region is disposed between a plurality of the first regions.

4. The memory device according to claim 2 , wherein
the first insulating layer includes a plurality of the first regions whose upper surfaces are in a lower position than that of the second region is, on each of both sides of the second region, and the third region is disposed between a plurality of the first regions.

5. The memory device according to claim 2 , wherein
a length of the gate electrode layer in a first direction from the second region to the third region along the upper surface of the second region is larger than a length in the first direction of the semiconductor layer on the second region.

6. The memory device according to claim 2 , wherein
the semiconductor layer comprises an impurity layer at both ends of the semiconductor layer.

7. The memory device according to claim 1 , wherein
the first insulating layer includes a plurality of the first regions whose upper surfaces are in a lower position than that of the second region is, on at least one side of the second region, and the third region is disposed between a plurality of the first regions.

8. The memory device according to claim 7 , wherein
a plurality of the first regions have an aspect ratio of a sidewall surface and the upper surface which is larger than 1.

9. The memory device according to claim 7 , wherein
a length of the gate electrode layer in a first direction from the second region to the third region along the upper surface of the second region is larger than a length in the first direction of the semiconductor layer on the second region.

10. The memory device according to claim 7 , wherein
the semiconductor layer comprises an impurity layer at both ends of the semiconductor layer.

11. The memory device according to claim 1 , wherein
the first insulating layer includes a plurality of the first regions whose upper surfaces are in a lower position than that of the second region is, on each of both sides of the second region, and the third region is disposed between a plurality of the first regions.

12. The memory device according to claim 11 , wherein
a plurality of the first regions have an aspect ratio of a sidewall surface and the upper surface which is larger than 1.

13. The memory device according to claim 1 , wherein
a length of the gate electrode layer in a first direction from the second region to the third region along the upper surface of the second region is larger than a length in the first direction of the semiconductor layer on the second region.

14. The memory device according to claim 1 , wherein
the semiconductor layer comprises an impurity layer at both ends of the semiconductor layer.

15. The memory device according to claim 14 , wherein
the semiconductor layer has an impurity concentration between the impurity layers which is 10 times or more less than that of the impurity layer.

Assignees

• Toshiba Memory Corp

Inventors

• Sakuma Kiwamu
• Ikeda Keiji
• Saitoh Masumi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic