Low power analog to digital converter

Patent metadata

Field	Value
Publication number	US-2016233879-A1
Application number	US-201514705805-A
Country	US
Kind code	A1
Filing date	May 6, 2015
Priority date	Dec 19, 2012
Publication date	Aug 11, 2016
Grant date	—

Abstract

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

First claim

1 . An apparatus comprising:
at least two analog multiplexers; at least two analog to digital converters (ADC) to receive outputs of the at least two analog multiplexers and to generate corresponding at least two digital outputs; and a digital multiplexer to receive the at least two digital outputs, and to selectively provide a logic output according to one of the selected at least two digital outputs.

2 . The apparatus of claim 1 , wherein at least one of the at least two ADCs comprises a sigma-delta modulator.

3 . The apparatus of claim 2 , wherein the sigma-delta modulator comprises:
a first capacitor; and at least two switches, one of which is operable to couple an input analog signal to the first capacitor, and the other switch is operable to couple a reference signal or a logic signal to the first capacitor.

4 . The apparatus of claim 3 , wherein the sigma-delta modulator comprises:
an integrator having an input coupled to the first capacitor; a multiplexer operable to select an output of the integrator or an inverse of the output of the integrator; and a sampler to sample the output of the multiplexer.

5 . The apparatus of claim 4 , wherein an output of the sampler is one of the at least two digital outputs, and wherein the output of the sampler is used to select one of the reference signal or the logic signal for coupling to the other switch.

6 . The apparatus of claim 4 , wherein the integrator comprises:
an amplifier having an input coupled to the first capacitor; a first switch coupled to the input of the amplifier and an output of the amplifier; a second capacitor coupled to the output of the amplifier; and a second switch coupled to the second capacitor and the input of the amplifier.

7 . The apparatus of claim 6 , wherein the amplifier is one of:
a cascode inverter amplifier; an inverter, or an operational amplifier.

8 . The apparatus of claim 6 , wherein the first and second switches are controllable by two different phases of a clock signal.

9 . The apparatus of claim 3 , wherein the first capacitor is a switched capacitor subtractor.

10 . The apparatus of claim 1 comprises a counter to count a number of ones or zeros in the logic output to generate a digital code.

11 . The apparatus of claim 1 , wherein each of the at least two analog multiplexers is controllable by a separate select line.

12 . A method comprising:
coupling an input analog signal to a first capacitor during a first phase of a clock signal; closing a first switch of an integrator during the first phase such that an input and an output of an amplifier of the integrator are electrically shorted; coupling one of a reference signal or a logic signal to the first capacitor during a second phase of the clock signal; and closing a second switch of the integrator during the second phase, the second switch to couple the input and the output of the amplifier via a second capacitor.

13 . The method of claim 12 , comprises:
controlling a third switch using the first phase, the third switch to couple one of the reference signal or the logic signal to the first capacitor during a chopping mode; and controlling a fourth switch using the second phase, the fourth switch to couple the input analog signal to the first capacitor during the chopping mode.

14 . The method of claim 12 , wherein coupling one of the reference signal or the logic signal to the first capacitor is according to a logic state of the output of the amplifier.

15 . An apparatus comprises:
a first analog to digital converter (ADC) including:
a first capacitor; and
at least two switches, one of which is operable to couple an input analog signal to the first capacitor of the first ADC, and the other switch is operable to couple a first reference signal or a first logic signal to the first capacitor of the first ADC; and
a second ADC including:
a first capacitor; and
at least two switches, one of which is operable to couple the input analog signal to the first capacitor of the second ADC, and the other switch is operable to couple a second reference signal or a second logic signal to the first capacitor of the second ADC.

16 . The apparatus of claim 15 , wherein one of the switches of the first ADC, which is operable to couple the input analog signal to the first capacitor of the first ADC, is controllable by a first phase of a clock signal, and wherein one of the switches of the second ADC, which is operable to couple the input analog signal to the first capacitor of the second ADC, is controllable by a second phase of the clock signal.

17 . The apparatus of claim 16 , wherein the other switch of the first ADC, which is operable to couple the first reference signal or the first logic signal to the first capacitor of the first ADC, is controllable by the second phase, and wherein the switch of the second ADC, which is operable to couple the second reference signal or the second logic signal to the first capacitor of the second ADC, is controllable by the first phase.

18 . The apparatus of claim 15 , wherein each of the first and second ADCs include:
an integrator having an input coupled to the first capacitor of the respective ADC; a multiplexer operable to select an output of the integrator or an inverse of the output of the integrator; and a sampler to sample the output of the multiplexer.

19 . The apparatus of claim 18 , wherein the integrator comprises:
an amplifier having an input coupled to the first capacitor; a first switch coupled to the input of the amplifier and an output of the amplifier; a second capacitor coupled to the output of the amplifier; and a second switch coupled to the second capacitor and the input of the amplifier.

20 . The apparatus of claim 15 , wherein the first capacitors of the first and second ADCs are switched capacitor subtractors, respectively.

Assignees

• Intel Corp

Inventors

• Oshita Takao
• Geannopoulos George L
• Duarte David E
• Hodgson J Keith
• Ayers James S
• Kornfeld Avner
• Douglas Jonathan P

Classifications

• H03M3/34 Primary

  by chopping · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title