Input device receiver with delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-10061415-B2
Application number	US-201615199276-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A processing system, and associated input device and method are disclosed suitable for reducing a receiver size within the input device. The processing system comprises a delta-sigma modulator comprising one or more input nodes configured to receive a signal based on a sensor signal received from at least a first sensor electrode of the plurality of sensor electrodes. The delta-sigma modulator further comprises an integrator coupled with the one or more input nodes and configured to produce an integration signal, a quantizer coupled with an output of the integrator and configured to quantize the integration signal, and a feedback digital-to-analog converter (DAC) controlled based by the quantizer. The processing system further comprises a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

First claim

What is claimed is:

1. A processing system for an input device comprising a plurality of sensor electrodes, the processing system comprising:
a current conveyor configured to receive a sensor signal from a first sensor electrode of the plurality of sensor electrodes, and to output a mirrored current of the sensor signal;
a mixer configured to downconvert the mirrored current, and to output a processed sensor signal;
a delta-sigma modulator comprising:
one or more input nodes configured to receive the processed sensor signal;
an integrator coupled with the one or more input nodes and configured to produce an integration signal;
a quantizer coupled with an output of the integrator and configured to quantize the integration signal; and
a feedback digital-to-analog converter (DAC) controlled based by the quantizer; and

a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

2. The processing system of claim 1 , wherein the delta-sigma modulator further comprises:
a common-mode feedback circuit coupled with the one or more input nodes and configured to mitigate a common-mode current produced by the current conveyor.

3. The processing system of claim 1 , wherein the current conveyor comprises a single-ended input and the delta-sigma modulator comprises fully-differential inputs.

4. The processing system of claim 1 , wherein the delta-sigma modulator is a continuous-time modulator, wherein the digital filter is a low-pass filter, and wherein the quantizer is a single-bit quantizer.

5. The processing system of claim 1 , wherein the integrator is a passive integrator.

6. The processing system of claim 5 , wherein the passive integrator comprises a capacitance of the first sensor electrode.

7. An input device, comprising:
a plurality of sensor electrodes; and
a processing system coupled with the plurality of sensor electrodes and comprising:
a current conveyor configured to receive a sensor signal from a first sensor electrode of the plurality of sensor electrodes, and to output a mirrored current of the sensor signal;
a mixer configured to downconvert the mirrored current, and to output a processed sensor signal;
a delta-sigma modulator comprising:
one or more input nodes configured to receive the processed signal;
an integrator coupled with the one or more input nodes and configured to produce an integration signal;
a quantizer coupled with an output of the integrator and configured to quantize the integration signal; and
a feedback digital-to-analog converter (DAC) controlled based by the quantizer; and

a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

8. The input device of claim 7 , wherein the delta-sigma modulator further comprises:
a common-mode feedback circuit coupled with the one or more input nodes and configured to mitigate a common-mode current produced by the current conveyor.

9. The input device of claim 7 , wherein the current conveyor comprises a single-ended input and the delta-sigma modulator comprises fully-differential inputs.

10. The input device of claim 7 , wherein the delta-sigma modulator is a continuous-time modulator, wherein the digital filter is a low-pass filter, and wherein the quantizer is a single-bit quantizer.

11. The input device of claim 7 , wherein the integrator is a passive integrator.

12. The input device of claim 11 , wherein the passive integrator comprises a capacitance of the first sensor electrode.

13. A method comprising:
mirroring, using a current conveyor, a current of a sensor signal received from a first sensor electrode of a plurality of sensor electrodes;
downconverting, using a mixer, the mirrored current to produce a processed sensor signal;
integrating a signal based on the processed sensor signal to produce an integration signal;
quantizing the integration signal;
controlling a feedback digital-to-analog converter (DAC) based on the quantization of the integration signal, the feedback DAC coupled with one or more input nodes; and
mitigating a quantization noise using a digital filter.

14. The method of claim 13 , further comprising:
mitigating, using a common-mode feedback circuit coupled with the one or more input nodes, a common-mode current produced by the current conveyor.

15. The method of claim 13 , wherein the current conveyor comprises a single-ended input and a delta-sigma modulator comprises fully-differential inputs.

16. The method of claim 13 , wherein receiving the sensor signal, integrating the signal, quantizing the integration signal, and controlling the feedback DAC are performed by a delta-sigma modulator, wherein the delta-sigma modulator is a continuous-time modulator, wherein the digital filter is a low-pass filter, and wherein the quantizer is a single-bit quantizer.

17. The method of claim 13 , wherein integrating the signal is performed using a passive integrator.

18. The processing system of claim 1 , wherein the mirrored current output by the current conveyor is scaled by a non-unity value of a factor A.

19. The processing system of claim 1 , wherein the mixer is configured to downconvert the mirrored current to approximately direct current (DC) levels.

20. The processing system of claim 1 , wherein the mixer comprises one of a square-wave mixer, a harmonic rejection mixer, and a sinusoidal mixer.

Assignees

• Synaptics Inc

Inventors

• Bohannon Eric Scott
• Bell Jr Marshall J
• Yang Yihong

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/34

  by chopping · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M1/0626

  by filtering · CPC title