Delta sigma modulator with dynamic error cancellation

Patent metadata

Field	Value
Publication number	US-9660665-B2
Application number	US-201615226436-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Aug 6, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

First claim

What is claimed is:

1. A delta sigma modulator comprising:
a first input port and a second input port, the first input port and the second input port configured to receive a differential input signal;
a digital to analog converter (DAC) coupled to the first input port and the second input port, and configured to receive a differential feedback signal and a plurality of selection signals;
a loop filter coupled to the first input port and the second input port, and configured to generate a differential filtered signal in response to a differential error signal, the differential error signal is proportional to a difference in the differential input signal and the differential feedback signal;
a quantizer coupled to the loop filter and configured to generate a quantized output signal in response to the differential filtered signal; and
a modified data weighted averaging (DWA) block coupled between the quantizer and the DAC, the modified DWA block configured to receive a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals, and configured to generate the plurality of selection signals in response to the chop clock, the regular clock, the quantized output signal and the plurality of selection index signals, wherein a selection index signal of the plurality of selection index signals is dependent on previously generated plurality of selection signals.

2. The delta sigma modulator of claim 1 , wherein the previously generated plurality of selection signals are generated in a previous state of the regular clock.

3. The delta sigma modulator of claim 1 further comprising a reset filter coupled to the quantizer and configured to generate a digital output signal in response to the quantized output signal and a plurality of filter coefficients.

4. The delta sigma modulator of claim 1 , wherein the modified DWA block comprises a plurality of transition counters, each transition counter of the plurality of transition counters comprising:
a transition detect gate configured to generate a state signal in response to a set of previously generated selection signals of the plurality of previously generated selection signals;
a first multiplier configured to multiply the state signal, a delayed chop clock, and a weighted primary coefficient to generate a first intermediate signal;
a primary filter coupled to the first multiplier, and configured to filter the first intermediate signal to generate a second intermediate signal;
a second multiplier configured to multiply the second intermediate signal and the chop clock to generate a third intermediate signal; and
a third multiplier configured to multiply the third intermediate signal and a selection index signal of the plurality of selection index signals to generate an indexed signal.

5. The delta sigma modulator of claim 4 , wherein the modified DWA block further comprises a vector quantizer, the vector quantizer configured to generate the plurality of selection signals in response to the indexed signal received from each transition counter of the plurality of transition counters and the quantized output signal.

6. The delta sigma modulator of claim 4 , wherein the second intermediate signal is proportional to a number of transitions in a phase of the chop clock, and the weighted primary coefficient at a defined state of regular clock is derived from the plurality of filter coefficients.

7. The delta sigma modulator of claim 4 , wherein each transition counter further comprises:
a secondary filter configured to filter a selection signal of the plurality of selection signal to generate a fourth intermediate signal;
a multiplier configured to multiply the indexed signal and a weighted secondary coefficient to generate a fifth intermediate signal; and
a summer coupled to the secondary filter, and configured to sum the fourth intermediate signal and the fifth intermediate signal to generate a weighted indexed signal.

8. The delta sigma modulator of claim 7 , wherein the vector quantizer is configured to generate the plurality of selection signals in response to the weighted indexed signal received from each transition counter of the plurality of transition counters and the quantized output signal.

9. The delta sigma modulator of claim 1 , wherein the DAC includes a plurality of DAC elements, at least one DAC element of the plurality of DAC elements comprises:
a first switch coupled to the first input port;
a second switch coupled to the second input port, the first switch and the second switch configured to receive the differential input signal; and
a current source coupled between a ground terminal and the first switch and the second switch, wherein the first switch and the second switch configured to be activated by a selection signal of the plurality of selection signals, and an inverted selection signal respectively, and wherein a logic of the selection signal is inverted to generate the inverted selection signal.

10. The delta sigma modulator of claim 1 , wherein the loop filter further comprises:
an operational amplifier having an inverting terminal and a non-inverting terminal, the operational amplifier configured to generate a differential output signal in response to the differential error signal;
a first chopper coupled to the operational amplifier, and configured to generate the differential filtered signal at a first output terminal and a second output terminal in response to the differential output signal;
a second chopper coupled to the inverting terminal of the operational amplifier;
a first feedback capacitor coupled between the second chopper and the first output terminal;
a third chopper coupled to the non-inverting terminal of the operational amplifier; and
a second feedback capacitor coupled between the third chopper and the second output terminal.

11. The delta sigma modulator of claim 1 further comprising:
a fourth chopper coupled to the first input port and the second input port, and configured to chop the differential input signal, and after chopping, configured to provide the differential feedback signal to the DAC and to provide the differential error signal to the loop filter; and
a fifth chopper coupled between the modified DWA block and the DAC, and configured to chop the plurality of selection signals, and after chopping, configured to provide the plurality of selection signals to the DAC.

12. The delta sigma modulator of claim 1 further comprising a sixth chopper coupled between the quantizer and the reset filter, the sixth chopper configured to chop the quantized output signal, and after chopping, configured to provide the quantized output signal to the reset filter.

13. The delta sigma modulator of claim 12 , wherein the first chopper, the second chopper, the third chopper, the fourth chopper, the fifth chopper and the sixth chopper are configured to operate at the chop clock.

14. A method comprising:
receiving a differential input signal;
receiving a differential feedback signal and a plurality of selection signals in a digital to analog converter (DAC);
generating a differential filtered signal in response to a differential error signal, the differential error signal is proportional to a difference in the differential input signal and the differential feedback signal;
quantizing the differential filtered signal to generate a quantized output signal; and
generating the plurality of selection signals in response to the quantized output signal, a chop clock, a regular clock and a plurality of selection index signals, wherein a selection index signal of the plurality of selection index signals is depen

Assignees

• Texas Instruments Inc

Inventors

• Miglani Eeshan
• Gunasekaran Karthikeyan
• GOWDHAMAN Santhosh Kumar
• Dusad Shagun

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M1/747 Primary

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title