Low power analog to digital converter

Patent metadata

Field	Value
Publication number	US-10033402-B2
Application number	US-201615265730-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Dec 19, 2012
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

First claim

We claim:

1. An apparatus comprising:
a reference generator to provide a reference voltage;
a sigma-delta modulator coupled to the reference generator, wherein the sigma-delta modulator is to receive an analog signal; and
a finite state machine (FSM) coupled to an output of the sigma-delta modulator, wherein the FSM is to provide a digital code representing the analog signal; and a first multiplexer coupled to the reference generator.

2. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an amplifier and a circuit to perform auto zero correction of the amplifier.

3. The apparatus of claim 2 , wherein the sigma-delta modulator comprises a chopper which is operable to cancel common-mode noise from the amplifier.

4. The apparatus of claim 2 , wherein the amplifier and the circuit are part of an integrator.

5. The apparatus of claim 2 , wherein the amplifier comprises an inverter.

6. The apparatus of claim 1 , wherein the first multiplexer is controlled by an input of the FSM.

7. The apparatus of claim 6 , wherein the first multiplexer is to selectively provide one of the reference voltage or a digital bit to a first switch.

8. The apparatus of claim 7 , comprises a first capacitive device coupled to the first switch and the amplifier.

9. The apparatus of claim 8 , comprises a second switch to receive the analog signal, wherein the second switch is coupled to the first capacitive device.

10. The apparatus of claim 9 comprises a third switch coupled to an output of the amplifier and the second switch.

11. The apparatus of claim 10 comprises:
a fourth switch coupled to the second switch; and
a second capacitive device coupled in series with the fourth switch, wherein the second capacitive device is also coupled to an output of the amplifier.

12. The apparatus of claim 11 comprises a buffer coupled to an output of the amplifier.

13. The apparatus of claim 12 comprises a second multiplexer coupled to an output of the buffer.

14. The apparatus of claim 13 comprises a sampler coupled to an output of the second multiplexer, wherein an output of the sampler is to control the first multiplexer.

15. The apparatus of claim 1 , wherein the FSM includes at least two counters.

16. An apparatus comprising:
means for coupling an input analog signal to a first capacitor during a first phase of a clock signal;
means for closing a first switch of an integrator during the first phase such that an input and an output of an amplifier of the integrator are electrically shorted;
means for coupling one of a reference signal or a logic signal to the first capacitor during a second phase of the clock signal; and
means for closing a second switch of the integrator during the second phase, the second switch to couple the input and the output of the amplifier via a second capacitor.

17. The apparatus of claim 16 comprises means for controlling a third switch using the first phase, the third switch to couple one of the reference signal or the logic signal to the first capacitor during a chopping mode.

18. The apparatus of claim 17 comprises means for controlling a fourth switch using the second phase, the fourth switch to couple the input analog signal to the first capacitor during the chopping mode.

19. The apparatus of claim 18 , wherein the means for coupling one of the reference signal or the logic signal to the first capacitor uses a logic state of the output of the amplifier.

20. An apparatus comprising:
an amplifier having an input and an output, wherein the amplifier is a single-ended amplifier;
a first switch coupled to the input and the output;
a first capacitive device;
a second switch coupled in series with the first capacitive device, wherein the first capacitive device and the second switch are together coupled to the input and the output;
a buffer directly coupled to the output;
a multiplexer coupled to an output of the buffer; and
a second capacitive device coupled to the input.

21. The apparatus of claim 20 , comprises a third switch coupled to the second capacitive device.

22. The apparatus of claim 21 comprises a fourth switch coupled to the second capacitive device.

23. The apparatus of claim 21 wherein the multiplexer is a first multiplexer, wherein the apparatus comprises a second multiplexer coupled to the third switch, and wherein the second multiplexer is to provide one of a reference voltage, logic high, or a logic low.

24. The apparatus of claim 23 wherein the first multiplexer is to provide as output to a sampler one of an inverted version of the output of the buffer or the output of the buffer.

25. An apparatus comprising:
an inverter having an input and output;
a first capacitive device coupled to the input of the inverter, wherein one terminal of the capacitive device is switchably coupled to one of at least two nodes; and
a buffer directly coupled to the output of the inverter and a multiplexer coupled to an output of the buffer.

26. The apparatus of claim 25 comprises:
a second capacitive device;
a first switch coupled to the input and the output; and
a second switch coupled in series with the second capacitive device, wherein the second capacitive device and the second switch are together coupled to the input and the output.

27. The apparatus of claim 26 comprises:
a third switch coupled to the second capacitive device; and
a fourth switch coupled to the second capacitive device.

28. The apparatus of claim 27 wherein the multiplexer is a first multiplexer, wherein the first multiplexer is to provide as output to a sampler one of an inverted version of the output of the buffer or the output of the buffer, comprises:
a second multiplexer coupled to the third switch, wherein the second multiplexer is to provide one of a reference voltage, logic high, or a logic low.

Assignees

• Intel Corp

Inventors

• Oshita Takao
• Geannopoulos George L
• Duarte David E
• Hodgson J Keith
• Ayers James S
• Kornfeld Avner
• Douglas Jonathan P

Classifications

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title