Chopper stabilized sigma delta ADC

Patent metadata

Field	Value
Publication number	US-9685967-B1
Application number	US-201615259205-A
Country	US
Kind code	B1
Filing date	Sep 8, 2016
Priority date	Sep 8, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A ΣΔ ADC includes a forward path, a feedback path, and offset compensation circuitry. The forward path is configured to convert an analog input signal to a digital output signal and includes analog chopper circuitry configured to shift the analog input signal to a chopper frequency to generate a chopped analog signal. The feedback path includes a ΣΔ DAC configured to convert a digital offset compensation signal configured to compensate for offset error in the analog input signal to an analog feedback signal that is subtracted from a forward path signal. The offset compensation circuitry is configured to accumulate a chopped digital signal from the forward path to generate a digital offset error signal; add the digital offset error signal to the digital output signal to generate the digital offset compensation signal; and provide the digital offset compensation signal to the ΣΔ DAC.

First claim

What is claimed is:

1. A sigma delta analog to digital converter (ΣΔ ADC) comprising:
a forward path configured to convert an analog input signal to a digital output signal, wherein the forward path comprises analog chopper circuitry configured to shift the analog input signal from an original frequency to a chopper frequency to generate a chopped analog signal;
a feedback path comprising a ΣΔ digital to analog converter (DAC) configured to convert a digital offset compensation signal configured to compensate for offset error in the analog input signal to an analog feedback signal that is subtracted from a forward path signal; and
offset compensation circuitry configured to:
accumulate a chopped digital signal from the forward path to generate a digital offset error signal;
combine the digital offset error signal with the digital output signal to generate the digital offset compensation signal; and
provide the digital offset compensation signal to the ΣΔ DAC.

2. The ΣΔ ADC of claim 1 , wherein the forward path comprises i) comparator circuitry configured to generate a comparator signal, ii) digital integrator circuitry configured to generate a digital integrated signal, and iii) second summation circuitry configured to add the comparator signal to the digital integrated signal to stabilize the digital output signal, further wherein the chopped digital signal comprises a chopped comparator signal at the chopper frequency.

3. The ΣΔ ADC of claim 1 , wherein the analog input signal comprises an output of a fast switching sensor.

4. The ΣΔ ADC of claim 1 , wherein the compensation circuitry comprises digital chopper circuitry configured to shift the digital offset error signal from the chopper frequency to the original frequency to generate an unchopped digital offset error signal that is combined with the digital output signal to generate the digital offset compensation signal at the original frequency.

5. The ΣΔ ADC of claim 4 , wherein:
the forward path signal comprises the chopped analog input signal; and
the feedback path comprises second analog chopper circuitry configured to shift the analog feedback signal from the original frequency to the chopper frequency to generate a chopped analog feedback signal that is subtracted from the chopped analog input signal.

6. The ΣΔ ADC of claim 4 , wherein the forward path signal comprises the analog input signal at the original frequency.

7. An offset compensation circuitry for use in a feedback path of a sigma delta analog to digital converter (ΣΔ ADC), wherein the ΣΔ ADC comprises a forward path comprising forward path circuitry configured to convert an analog input signal having a signal component and an offset error component to a digital output signal, wherein the forward path comprises first analog chopper circuitry configured to shift the analog input signal from an original frequency to a chopper frequency to generate a chopped analog input signal, and wherein the feedback path comprises a ΣΔ digital to analog converter (DAC), and wherein the ΣΔ ADC is configured to subtract an analog feedback signal generated by the ΣΔ DAC from a forward path signal, the offset compensation circuitry comprising:
first summation circuitry;
a signal path disposed between the forward path and the first summation circuitry, the signal path configured to conduct a chopped first digital signal from the forward path to the first summation circuitry;
accumulation circuitry;
a compensation path disposed between the signal path and the accumulation circuitry, wherein the accumulation circuitry is configured to accumulate a chopped second digital signal from the forward path to generate a digital offset error signal that approximates the offset error component; and
wherein the first summation circuitry is configured to add the digital offset error signal to the first digital signal to generate a digital offset compensation signal, wherein the digital offset compensation signal is input to the ΣΔ DAC.

8. The offset compensation circuitry of claim 7 , wherein the signal path comprises a first digital chopper configured to shift the digital output signal to the chopper frequency to generate the first digital signal, such that the digital offset compensation signal is at the chopper frequency.

9. The offset compensation circuitry of claim 7 , wherein:
the compensation path comprises a third digital chopper configured to shift an output of the accumulation circuitry to the original frequency to generate the digital offset compensation signal, such that the digital offset compensation signal is at the original frequency;
the feedback path comprises a second analog chopper circuitry configured to shift an output of the ΣΔ DAC to the chopper frequency to generate the analog feedback signal.

10. The offset compensation circuitry of claim 7 , wherein the accumulation circuitry comprises third summation circuitry configured to add a chopped digital signal having the signal component at the chopper frequency to a prior value of the digital offset error signal to generate the digital offset error signal.

11. The offset compensation circuitry of claim 10 wherein the accumulation circuitry is configured to output a selected number of most significant bits of the digital offset error signal and while the prior value of the digital offset error comprises all bits of the digital offset error signal.

12. The offset compensation circuitry of claim 7 , wherein the forward path comprises i) comparator circuitry configured to generate a comparator signal, ii) digital integrator circuitry configured to generate a digital integrated signal, and iii) second summation circuitry configured to add the comparator signal to the digital integrated signal to stabilize the digital output signal, further wherein:
the signal path comprises first digital chopper circuitry configured to shift the digital output signal to the chopper frequency to generate the first digital signal;
the compensation path comprises second digital chopper circuitry, wherein the second digital chopper circuitry is configured to shift the comparator signal to the chopper frequency to generate the chopped second digital signal.

13. The offset compensation circuitry of claim 12 , wherein the forward path comprises second analog chopper circuitry configured to shift a signal component of the forward path signal back to the original frequency while shifting the offset error component to the chopper frequency to generate second forward path signal, and further wherein the comparator inputs the second forward path signal such that the comparator is outside a chopping loop defined by the first analog chopper circuitry and the second analog chopper circuitry.

14. The offset compensation circuitry of claim 7 , wherein the forward path comprises i) comparator circuitry configured to generate a chopped comparator signal from a chopped analog signal in the forward path having the chopper frequency, ii) first digital forward path digital chopper circuitry configured to shift the chopped comparator signal to the original frequency to generate a comparator signal, iii) digital integrator circuitry configured to integrate the comparator signal to generate a digital integrated signal, iv) second summation circuitry configured to add the comparator signal to the digital integrated signal to generate the digital output signal, further wherein:
the first digital signal comprises the digital output signal; and
the chopped second digital signal comprises the chopped comparator signal.

15. The offset compensation circuitry of claim 14 , wherein the comparator is

Assignees

• Infineon Technologies Ag

Inventors

• Motz Mario
• Stoica Dan
• Gheorghe Andrei

Classifications

• H03M3/34

  by chopping · CPC title

• H03M3/356 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title