Wafer back-side polishing system and method for integrated circuit device manufacturing processes

Patent metadata

Field	Value
Publication number	US-2016190023-A1
Application number	US-201615060807-A
Country	US
Kind code	A1
Filing date	Mar 4, 2016
Priority date	Feb 17, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

First claim

1 . A wafer polishing process, comprising:
forming integrated circuit component devices on a front side of a wafer; and after the integrated circuit component devices have been formed on the front side of the wafer, polishing a first portion of a back side of the wafer by using a first polishing pad having a first grit and buffing a second portion of the back side of the wafer using a second buffing pad having a second grit, the second grit being less than the first grit.

2 . The wafer polishing process of claim 1 , wherein the first portion corresponds to a central area of the back side of the wafer and the second portion corresponds to a peripheral area of the back side of the wafer, the first and second portions being non-overlapping with one another.

3 . The wafer polishing process of claim 2 , wherein the peripheral area comprises a bevel region of the wafer.

4 . The wafer polishing process of claim 3 , further comprising polishing a portion of the bevel region, wherein the portion of the bevel region is at least half a total surface area of the bevel region.

5 . The wafer polishing process of claim 1 , further comprising:
after polishing the first portion, using a first buffing pad, which has a third grit that is finer than the first grit, to buff the first portion.

6 . The wafer polishing process of claim 5 , wherein the first buffing pad has a grit of 20,000 or finer.

7 . The wafer polishing process of claim 5 , wherein the first buffing pad is made from regularly shaped diamonds.

8 . The wafer polishing process of claim 1 , further comprising:
before buffing the second portion, using a second polishing pad, which has a fourth grit that is coarser than the second grit, to polish the second portion of the back side of the wafer.

9 . The wafer polishing process of claim 1 , wherein polishing the first portion or buffing the second portion comprising polishing or buffing with an abrasive tape that has a backing that is as soft or softer than polyurethane or polyethylene terephthalate (PET).

10 . The wafer polishing process of claim 1 , wherein polishing the first portion or buffing the second portion comprises irrigating the back side of the wafer with an aqueous solution comprising a surfactant or a chelating agent.

11 . A process, comprising:
forming integrated circuit component devices on a front side of a semiconductor substrate; after forming the integrated circuit component devices on the front side of the semiconductor substrate, polishing a central area on a back side of the semiconductor substrate using a first polishing pad and separately polishing a peripheral area on the back side of the semiconductor substrate using a second polishing pad; after polishing the central area on the back side of the semiconductor substrate, buffing the central area using a first buffing pad having a grit that is less than a grit of the first polishing pad; and after polishing the peripheral area on the back side of the semiconductor substrate, buffing the peripheral area using a second buffing pad having a grit that is less than a grit of the second polishing pad.

12 . The process of claim 11 , wherein the central area is non-overlapping with the peripheral area.

13 . The process of claim 11 , wherein the back side of the semiconductor substrate is polished and buffered to be a substantial planar surface after polishing and buffing the peripheral area and the central area.

14 . The process of claim 11 , further comprising:
prior to the polishing the central area, evaluating the semiconductor substrate to determine whether one or more focus spots are present on the semiconductor substrate; and selectively polishing the central area and selectively buffing the peripheral area based on whether one or more focus spots are present on the semiconductor substrate.

15 . A wafer polishing process, comprising:
forming integrated circuit component devices on a front side of a wafer; after forming the integrated circuit component devices on the front side of the wafer, polishing a first area on a back side of the wafer using a first polishing pad; and after polishing the first area on the back side of the wafer, buffing a second area on the back side of the wafer using a second buffing pad having a grit that is less than a grit of the first polishing pad.

16 . The wafer polishing process of claim 15 , further comprising
after forming the integrated circuit component devices on the front side of the wafer and prior to buffing the second area on the back side of the wafer, polishing the second area on the back side of the wafer using a second polishing pad, the second polishing pad having a grit that is coarser than the grit of the second buffing pad.

17 . The wafer polishing process of claim 15 , further comprising
after polishing the first area on the back side of the wafer, buffing the first area on the back side of the wafer using a first buffing pad, the first buffing pad having a grit that is finer than the grit of the first polishing pad.

18 . The wafer polishing process of claim 15 , wherein the back side of the wafer is polished and buffered to be a substantial planar surface after polishing the first area and buffing the second area.

19 . The wafer polishing process of claim 15 , wherein the first area corresponds to a central area of the back side of the wafer and the second area corresponds to a peripheral area of the back side of the wafer, the first and second areas being entirely non-overlapping with one another.

20 . The process of claim 15 , further comprising:
prior to the polishing the central area, evaluating the semiconductor substrate to determine whether one or more focus spots are present on the semiconductor substrate; and wherein polishing the central area and buffing the peripheral area are selectively performed based on whether one or more focus spots are present on the semiconductor substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Shen-Nan
• Tsai Teng-Chun
• Lu Hsin-Hsien
• Lin Chang-Sheng
• Lien Kuo-Cheng
• Lin Kuo-Yin
• Liu Wen-Kuei
• Chou Yu-Wei

Classifications

• H10P70/10

  Cleaning before device manufacture, i.e. Begin-Of-Line process · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0616

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• H10P72/0428

  Apparatus for mechanical treatment or grinding or cutting · CPC title