Test structure for monitoring liner oxidation

Patent metadata

Field	Value
Publication number	US-2016133531-A1
Application number	US-201414538811-A
Country	US
Kind code	A1
Filing date	Nov 12, 2014
Priority date	Nov 12, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

First claim

What is claimed is:

1 . A method of forming a device comprising:
providing a wafer, the wafer comprises a device layer having a main device region and a perimeter region; patterning the device layer with active and test patterns, wherein the test pattern comprises dummy patterns disposed in a test device area; processing the wafer, wherein the process forms at least one test device disposed in the perimeter region, and one or more active devices disposed in the main device region, wherein the test device determines a design window of the one or more active devices; and performing additional processing to complete forming the device.

2 . The method of claim 1 wherein forming the at least one test device comprises:
forming a resistor disposed on a substrate, wherein the resistor comprises a resistive element with first and second resistor ends;
forming an interlayer dielectric (ILD) layer on the substrate, wherein the ILD layer comprises upper and lower ILD layers, an etch stop layer is disposed between the upper and lower ILD layers; and
forming first and second resistor terminals disposed on the ILD layer, wherein the first and second resistor terminals are in communication with the first and second resistor ends.

3 . The method of claim 2 wherein:
the resistive element comprises an electrical resistance disposed between the first and second resistor terminals; and
the resistance is a designed resistance (RD).

4 . The method of claim 3 wherein the resistor comprises a polysilicon resistive element.

5 . The method of claim 2 wherein:
the lower interlayer dielectric (ILD) layer comprises a tetraethyl orthosilicate (TEOS) layer over a high aspect ratio process (HARP) dielectric layer; and
the upper ILD layer comprises a low k dielectric layer.

6 . The method of claim 5 wherein each of the resistor terminals comprises:
a lower resistor terminal, wherein
forming the lower resistor terminal includes forming a via opening in the lower interlayer dielectric (ILD) layer, and
forming a contact disposed in the via opening; and

an upper resistor terminal, wherein
forming the upper resistor terminal includes forming a trench in the upper ILD layer,
forming a barrier layer, wherein the barrier layer lines the trench without filling the trench, and
forming a metal pad disposed in the trench, wherein the metal pad fills the trench.

7 . The method of claim 6 wherein the barrier layer comprises a combination of conductive materials.

8 . The method of claim 7 wherein the barrier layer comprises tantalum nitride (TaN) and tantalum (Ta).

9 . The method of claim 6 wherein the lower resistor terminal comprises tungsten and the upper resistor terminal comprises copper.

10 . The method of claim 1 wherein:
the test device area comprises first, second and third regions;
the second region surrounds the first region; and
the third region surrounds the second region and defines the dimension of the test device area.

11 . The method of claim 10 wherein:
the first region comprises resistor terminals in communication with a resistive element;
the second region comprises an empty region devoid of dummy structures; and
the third region comprises a filled region filled with dummy structures.

12 . The method of claim 11 wherein:
the empty region comprises a designed size; and
the filled region comprises a designed dummy density.

13 . The method of claim 12 wherein a pairing of the empty region and filled region defines the design window.

14 . A method of forming a device comprising:
providing a substrate with a device layer; forming a resist layer on the device layer; providing a patterned reticle comprising active and test patterns corresponding to active and test devices, the test device determines a design window of the active device, wherein
the active patterns are disposed in a device region and the test patterns are disposed in a frame region, the frame region surrounds the device region,
the test patterns comprise a filled region filled with dummy structures,
the filled region surrounds an empty region devoid of dummy structures, and
the empty region surrounds an innermost region comprising a resistor, the resistor comprises a resistive element with first and second resistor ends;
patterning the resist layer using the reticle to form a patterned resist layer containing active and test patterns of the reticle;
performing an etch to pattern the device layer using the patterned resist layer; and performing additional processing to complete forming the device.

15 . The method of claim 14 comprising:
forming an interlayer dielectric (ILD) layer on the substrate, wherein the ILD layer comprises upper and lower ILD layers, an etch stop layer is disposed between the upper and lower ILD layers; and
forming first and second resistor terminals disposed on the ILD layer, wherein the first and second resistor terminals are in communication with the first and second resistor ends.

16 . The method of claim 15 wherein each of the resistor terminals comprises:
a lower resistor terminal, wherein
forming the lower resistor terminal includes forming a via opening in the lower interlayer dielectric (ILD) layer, and
forming a contact disposed in the via opening; and

an upper resistor terminal, wherein
forming the upper resistor terminal includes forming a trench in the upper ILD layer,
forming a barrier layer, wherein the barrier layer lines the trench without filling the trench, and
forming a metal pad disposed in the trench, wherein the metal pad fills the trench.

17 . The method of claim 16 wherein:
the barrier layer comprises a combination of conductive materials; and
the combination of conductive materials comprise tantalum nitride (TaN) and tantalum (Ta).

18 . The method of claim 16 wherein:
the resistive element comprises an electrical resistance disposed between the first and second resistor terminals; and
the resistance is a designed resistance (R D ).

19 . The method of claim 18 comprising:
testing the designed resistance (R D ) of the resistor to monitor barrier layer oxidation.

20 . The method of claim 14 wherein:
the empty region comprises a designed size;
the filled region comprises a designed dummy density; and
a pairing of the empty region and filled region defines the design window.

21 . A device comprising:
a wafer having active patterns disposed on a wafer substrate, wherein the active patterns are defined by a design window, the design window is determined by a test structure, wherein
the test structure comprises a filled region filled with dummy structures,
the filled region surrounds an empty region devoid of dummy structures,
the empty region surrounds an innermost region comprising a resistor having a designed resistance, and
a pairing of the empty region and filled region determines the design window.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Wang Daxiang
• Tan Juan Boon
• Lin Kemao
• Zhang Shaoqiang

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title

• H01L28/24

  Electricity · mapped topic

• H01L24/10

  Electricity · mapped topic