Semiconductor structure and method for manufacturing the same which increases the channel length

Patent metadata

Field	Value
Publication number	US-12598792-B2
Application number	US-202318176612-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Jul 22, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate and a gate. The substrate has an active region which includes a first doped region, a channel region and a second doped region arranged along a first direction. The gate includes a first conductive portion and at least two second conductive portions contacted with and connected to the first conductive portion, the first conductive portion is located above an upper surface of the substrate, the second conductive portions are located below the upper surface of the substrate, adjacent second conductive portions are arranged at intervals along the first direction, and the channel region surrounds sidewalls and a bottom surface of each of the second conductive portions. A method for manufacturing a semiconductor structure is also provided.

First claim

The invention claimed is:

1 . A semiconductor structure, comprising:
a substrate having an active region which comprises a first doped region, a channel region and a second doped region arranged along a first direction; and a gate comprising a first conductive portion and at least two second conductive portions contacted with and connected to the first conductive portion, the first conductive portion located above an upper surface of the substrate, the second conductive portions located below the upper surface of the substrate, adjacent second conductive portions arranged at intervals along the first direction, and the channel region surrounding sidewalls and a bottom surface of each of the second conductive portions; and an insulating structure located in the active region and located between the adjacent second conductive portions; and a projection of the first conductive portion on a surface of the substrate partially coincides with a projection of the first doped region on the surface of the substrate and partially coincides with a projection of the second doped region on the surface of the substrate, and a projection of each of the second conductive portions on the surface of the substrate is located between the projection of the first doped region on the surface of the substrate and the projection of the second doped region on the surface of the substrate.

2 . The semiconductor structure of claim 1 , wherein along the first direction, a width of each of the second conductive portions is identical.

3 . The semiconductor structure of claim 1 , wherein in a direction perpendicular to a surface of the substrate, heights of several of the second conductive portions are identical.

4 . The semiconductor structure of claim 1 , wherein along the first direction, heights of several of the second conductive portions are sequentially increased.

5 . The semiconductor structure of claim 1 , wherein along the first direction, widths of the adjacent second conductive portions are sequentially decreased.

6 . The semiconductor structure of claim 4 , wherein along the first direction, widths of the adjacent second conductive portions are sequentially decreased.

7 . The semiconductor structure of claim 1 , wherein in a direction perpendicular to a surface of the substrate, a height of each of the second conductive portions is identical to a height of a corresponding part of the first conductive portion contacted with the second conductive portion.

8 . The semiconductor structure of claim 1 , wherein along the first direction, a width of the insulating structure is less than or equal to one-third of a spacing between the second conductive portions.

9 . The semiconductor structure of claim 1 , wherein in a direction perpendicular to a surface of the active region, a spacing between a top surface of the insulating structure and the first conductive portion is greater than or equal to one-fifth of a thickness of each of the second conductive portions.

10 . The semiconductor structure of claim 1 , wherein the insulating structure located between the adjacent second conductive portions comprises a plurality of insulating structures arranged at intervals.

11 . The semiconductor structure of claim 10 , wherein each of the second conductive portions comprises a first sub-conductive portion and a second sub-conductive portion, the first sub-conductive portions are arranged in the substrate at intervals, the second sub-conductive portion is located between adjacent first sub-conductive portions and is also located between adjacent insulating structures, and along the first direction, a width of the first sub-conductive portion is greater than that of the second sub-conductive portion, and a bottom surface of the second sub-conductive portion is lower than a top surface of the insulating structure.

12 . The semiconductor structure of claim 1 , further comprising: a gate dielectric layer located between the gate and the substrate.

13 . The semiconductor structure of claim 1 , further comprising: a protective layer covering a top surface and sidewalls of the gate.

Assignees

• Changxin Memory Tech Inc

Inventors

• Cho Gyuseog

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/0221

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS] · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title