Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9899388-B2
Application number	US-201615191562-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Oct 7, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated circuit device, a plurality of grooves are formed in the inter-device isolation region of a substrate, a recess is formed by partially removing a surface of the substrate between the plurality of grooves, at least one fin-type active area is formed in a device region by etching the substrate in the device region and the inter-device isolation region, and the double-humped protrusion is formed from the surface of the substrate in the inter-device isolation region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate comprising a PMOS device region, an NMOS device region adjacent to the PMOS device region and an inter-device isolation region interposed between the PMOS device region and the NMOS device region;
a first fin-type active area protruding from the substrate, in one of the PMOS device region and NMOS device region;
a device isolation layer covering the substrate at the inter-device isolation region,
wherein, as viewed with respect to a vertical cross section extending between the PMOS device region and the NMOS device region:
an upper surface of the substrate at the inter-device isolation region comprises a double-humped protrusion, the double-humped protrusion comprising a first hump having a first peak, a second hump having a second peak and a recess disposed between the first peak and the second peak, the recess having a depth comprising a vertical distance from the lower most portion of the recess to a height of one of the first peak and second peak,
wherein the double-humped protrusion has a height comprising a vertical distance from a minimum height of a top surface of the substrate immediately adjacent to the double-humped protrusion to a top of one of the first peak and second peak, and the height of the double-humped protrusion is greater than the depth of the recess,

wherein the device isolation layer comprises:
an insulating liner covering a side wall of the first fin-type active area and the double-humped protrusion and being conformally formed on a top surface of the double-humped protrusion; and
a gap-fill insulating layer on the insulating liner, the gap-fill insulating layer covering the side wall of the first fin-type active area and covering the double-humped protrusion,

wherein the insulating liner comprises a first insulating liner and a second insulating liner that are sequentially stacked on the side wall of the first fin-type active area and the double-humped protrusion, and
wherein the first insulating liner is formed of a different material from the material of the second insulating liner.

2. The integrated circuit device of claim 1 , wherein the vertical cross section is taken in a direction perpendicular to a length direction of the first fin-type active area.

3. The integrated circuit device of claim 2 ,
wherein, with respect to the vertical cross section, side walls of the first hump are asymmetric with respect to the first peak, and
wherein, with respect to the vertical cross section, side walls of the second hump are asymmetric with respect to the second peak.

4. The integrated circuit device of claim 2 , wherein the upper surface of the substrate comprises valley portions at sides of the double-humped protrusion,
wherein, with respect to the vertical cross section, a lowest point of each of the valley portions is lower than a lowest point of the recessed top surface of the double-humped protrusion.

5. The integrated circuit device of claim 2 , wherein the integrated circuit device comprises a second fin-type active area adjacent to the first fin-type active area,
wherein, with respect to the vertical cross section, at least one of the first peak and the second peak is at the same level as a top surface of the substrate between the first and second fin-type active areas.

6. The integrated circuit device of claim 2 , wherein the integrated circuit device comprises a second fin-type active area adjacent to the first fin-type active area,
wherein, with respect to the vertical cross section, at least one of the first peak and the second peak is lower than a lowest point of the top surface of the substrate between the first and second fin-type active areas.

7. The integrated circuit device of claim 2 , wherein the integrated circuit device comprises a second fin-type active area adjacent to the first fin-type active area, and wherein, with respect to the vertical cross section, a lowest point of the recess is lower than a lowest point of the top surface of the substrate between the first and second fin-type active areas.

8. The integrated circuit device of claim 1 , wherein the insulating liner is formed of different material from the material of the gap-fill insulating layer.

9. An integrated circuit device comprising:
a substrate comprising a first device region, a second device region, and an inter-device isolation region between the first device region and the second device region;
a plurality of fin-type active areas protruding from the substrate, in the first device region and the second device region;
a device isolation layer disposed on the substrate at the inter-device isolation region between the first device region and the second device region;
wherein a surface of the substrate in the inter-device isolation region comprises a plurality of double-humped protrusions with a plurality of valley portions each between immediately neighboring pairs of the plurality of double-humped protrusions in the inter-device isolation region, a vertical depth of the valley portions being less than a height of the plurality of fin-type active areas;
wherein each of the plurality of double-humped protrusions comprises:
a first hump having a first peak;
a second hump having a second peak; and
a recessed top surface between the first hump and the second hump and lower than the first peak and the second peaks,

wherein, with respect to a vertical cross section, each of the plurality of double-humped protrusions is substantially symmetric about a vertical line extending through the recessed top surface, and
wherein the device isolation layer covers the plurality of double-humped protrusions and the plurality of valley portions.

10. The integrated circuit device of claim 9 , wherein the device isolation layer comprises a corrugated bottom surface facing the substrate,
wherein the corrugated bottom surface comprises a first protrusion surface and a second protrusion surface that protrude downward to different depths.

11. The integrated circuit device of claim 9 ,
wherein the recessed top surface is higher than a lowest point in the plurality of valley portions.

12. The integrated circuit device of claim 11 , wherein each of the plurality of valley portions and the recessed top surface are alternately disposed one by one along a direction extending from the first device region to the second device region.

13. The integrated circuit device of claim 11 , wherein the device isolation layer comprises a corrugated bottom surface facing the substrate, and
wherein the corrugated bottom surface comprises a first protrusion facing the plurality of valley portions and a second protrusion facing the recessed top surface, the first protrusion having a first depth from a top surface of the device isolation layer, and the second protrusion having a second depth from the top surface of the device isolation layer, wherein the second depth is less than the first depth.

14. The integrated circuit device of claim 11 , wherein each of the first hump and the second hump has both side walls of an asymmetric shape.

15. The integrated circuit device of claim 11 , wherein
sidewalls of the first hump have different lengths in a vertical direction, and
sidewalls of the second hump have different lengths in the vertical direction.

16. The integrated circuit device of claim 9 ,
wherein the fin type active areas of the plurality of fin-type active areas are spaced apart from each other by a first pitch, and
the double-humped protrusions of the plurality of double-humped protrusions are spaced apart

Assignees

• Kim Ki Il
• You Jung Gun
• Park Gi Gwan
• Samsung Electronics Co Ltd

Inventors

• Kim Ki Il
• You Jung Gun
• Park Gi Gwan

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H01L29/0657

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic