Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9960083-B1
Application number	US-201615342114-A
Country	US
Kind code	B1
Filing date	Nov 2, 2016
Priority date	Nov 2, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming a first gate structure on the first region and a second gate structure on the second region;
forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;
removing the first gate structure and the second gate structure to expose the substrate on the first region and the second region;
removing part of the substrate on the second region to form a first recess exposing the substrate;
removing part of the substrate on the first region to form a second recess exposing the substrate, wherein the depths of the first recess and the second recess are different and the substrate exposed by the first recess and the substrate exposed by the second recess comprise same material; and
forming a first metal gate on the first region and a second metal gate on the second region.

2. The method of claim 1 , further comprising:
forming a first mask on the first region;
using the first mask as mask to form the first recess;
removing the first mask;
using the ILD layer as mask to remove part of the substrate on the first region and part of the substrate on the second region.

3. The method of claim 2 , further comprising:
using the first mask to remove part of the substrate on the second region under a first etching time; and
using the ILD layer as mask to remove part of the substrate on the first region and part of the substrate on the second region under a second etching time, wherein the first etching time and the second etching time are the same.

4. The method of claim 2 , further comprising:
using the first mask to remove part of the substrate on the second region under a first etching time; and
using the ILD layer as mask to remove part of the substrate on the first region and part of the substrate on the second region under a second etching time, wherein the first etching time and the second etching time are different.

5. The method of claim 1 , further comprising:
forming a first mask on the first region;
using the first mask as mask to form the first recess;
removing the first mask;
forming a second mask on the second region; and
using the second mask as mask to form the second recess.

6. The method of claim 5 , further comprising:
using the first mask to form the first recess under a first etching time;
using the second mask to form the second recess under a second etching time, wherein the first etching time and the second etching time are different.

7. The method of claim 1 , wherein the first metal gate comprises:
a first work function metal layer; and
a first low resistance metal layer on the first work function metal layer.

8. The method of claim 7 , wherein the second metal gate comprises:
a second work function metal layer; and
a second low resistance metal layer on the second work function metal layer.

9. The method of claim 8 , wherein the first work function metal layer and the second work function metal layer comprise different conductive type.

10. The method of claim 1 , wherein the first metal gate and the second metal gate comprise different heights and a bottom surface of at least one of the first metal gate and the second metal gate is lower than a top surface of the substrate.

Assignees

• United Microelectronics Corp

Inventors

• Chen Tai-You
• Chen Cheng-Guo
• Wu Kun-Yuan
• Ho Chiu-Sheng
• Yang Po-Kang
• Lo Ta-Kang
• Chen Shang-Jr

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic