Memory system package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12593718-B2
Application number	US-202218090608-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Nov 24, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A memory system package structure and a manufacturing method thereof are disclosed. For example, the memory system package structure can include a memory chip, a memory controller and a distribution layer. The memory chip can include a first surface. The memory controller can be positioned on the first surface. The redistribution layer can be positioned on a side of the memory controller facing away from the memory chip. The memory chip and the memory controller can be electrically connected with the redistribution layer.

First claim

What is claimed is:

1 . A memory system package structure, comprising:
a memory chip including a first surface and a second surface opposite to the first surface; an electromagnetic shielding layer positioned on the second surface of the memory chip; a memory controller positioned on the first surface; and a redistribution layer positioned on a side of the memory controller facing away from the memory chip, the memory chip and the memory controller being electrically connected with the redistribution layer, wherein the memory chip further includes a plastic packaging layer that is positioned on the side of the memory controller facing away from the memory chip and covers sides of the memory controller, sides of the memory chip and the first surface of the memory chip in a direction towards the first surface of the memory chip, the redistribution layer is positioned on a side of the plastic packaging layer facing away from the first surface of the memory chip, and the electromagnetic shielding layer covers at least sides of the plastic packaging layer in the direction towards the first surface of the memory chip.

2 . The memory system package structure of claim 1 , wherein a top of the electromagnetic shielding layer is electrically connected with the redistribution layer.

3 . The memory system package structure of claim 1 , wherein the electromagnetic shielding layer further covers sides of the redistribution layer.

4 . The memory system package structure of claim 3 , wherein the electromagnetic shielding layer is electrically connected with the redistribution layer from the sides of the redistribution layer.

5 . The memory system package structure of claim 1 , wherein the electromagnetic shielding layer includes a metal layer and metal compound layers disposed on both sides of the metal layer.

6 . The memory system package structure of claim 1 , further comprising:
an exposed conductive pad disposed on the first surface of the memory chip; a first conductive structure positioned on the side of the memory controller facing away from the memory chip and electrically connected with the memory controller; and a second conductive structure positioned on the first surface and electrically connected with the conductive pad, wherein both the first conductive structure and the second conductive structure penetrate the plastic packaging layer in a direction perpendicular to the first surface, extend to the redistribution layer, and are electrically connected with the redistribution layer.

7 . The memory system package structure of claim 6 , further comprising metal solder balls positioned on a side of the redistribution layer facing away from the memory controller and electrically connected with the redistribution layer, wherein the memory chip and the memory controller are electrically connected with the metal solder balls through the redistribution layer.

8 . The memory system package structure of claim 7 , wherein the redistribution layer includes an insulating layer and a conductive layer formed in the insulating layer, and the conductive layer is electrically connected with the first conductive structure, the second conductive structure and the metal solder balls.

9 . The memory system package structure of claim 1 , further comprising an adhesive layer that is positioned between the first surface and the memory controller and is used for fixing the memory controller and the memory chip.

10 . The memory system package structure of claim 1 , wherein the memory chip and the memory controller are indirectly conductive to each other via the redistribution layer.

11 . The memory system package structure of claim 8 , wherein the electromagnetic shielding layer is electrically connected to the conductive layer.

12 . The memory system package structure of claim 1 , wherein the electromagnetic shielding layer includes a metal layer and metal compound layers that are formed on both sides of the metal layer.

13 . The memory system package structure of claim 12 , wherein the metal layer includes copper.

14 . The memory system package structure of claim 12 , wherein the metal compound layers include stainless steel.

15 . The memory system package structure of claim 6 , wherein the first conductive structure is disposed between the memory controller and the redistribution.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zeng Xinru
• Xu Zhen
• Qian Weisong
• Chen Peng

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10B80/00 Primary

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title