Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same

Patent metadata

Field	Value
Publication number	US-11538746-B2
Application number	US-201616349095-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Dec 23, 2016
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

First claim

What is claimed is:

1. A memory module in a system in package apparatus comprising:
a matrix including a landing surface;
a memory-die stack configured in a stair-step relationship and seated in the matrix, the memory-die stack including a first memory die and a subsequent memory die, the first memory die including an active surface and a backside surface and the subsequent memory die including an active surface and a backside surface, wherein the first memory die includes an orthogonal first bond wire that extends from the first memory die active surface and breaches the matrix landing surface, and the subsequent memory die includes an orthogonal subsequent bond wire that extends from the subsequent memory die active surface and breaches the matrix landing surface;
a processor first die disposed on the first memory die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the first memory die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
a spacer, separate from the matrix, and disposed within the matrix, the spacer disposed on the first memory die, and wherein the spacer is disposed laterally between the processor first die and the first memory die orthogonal first bond wire.

2. The memory module in a system in package apparatus of claim 1 , wherein the orthogonal first bond wire extends away from the first memory die active surface, and wherein the orthogonal subsequent bond wire extends away from the subsequent memory die active surface.

3. The memory module in a system in package apparatus of claim 1 , further including a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die, and an orthogonal second bond wire disposed on the second memory die, wherein the orthogonal second bond wire extends away from the second memory die.

4. The memory module in a system in package apparatus of claim 1 , further including:
a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die; and
a third memory die disposed on the second memory die active surface and between the second memory die and the subsequent memory die.

5. The memory module in a system in package apparatus of claim 1 , further including:
a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die; and
a third memory die disposed on the second memory die active surface and between the second memory die and the subsequent memory die, and wherein the third memory die is disposed on the subsequent memory die.

6. The memory module in a system in package apparatus of claim 1 , further comprising:
a redistribution layer that contacts the processor bump array and the first memory die orthogonal bond wire and the subsequent memory die orthogonal bond wire; and
a ball-grid array disposed on the redistribution layer.

7. The memory module in a system in package apparatus of claim 6 , further including a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die.

8. The memory module in a system in package apparatus of claim 6 , further including:
a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die; and
a third memory die disposed on the second memory die active surface and between the second memory die and the subsequent memory die.

9. The memory module in a system in package apparatus of claim 1 , wherein the processor first die includes memory controller hub function.

10. The memory module in a system in package apparatus of claim 1 , wherein the spacer is a second die.

11. A memory module in a system in package apparatus comprising:
a matrix including a landing surface;
a memory-die stack configured in a stair-step relationship and seated in the matrix, the memory-die stack including a first memory die and a subsequent memory die, the first memory die including an active surface and a backside surface and the subsequent memory die including an active surface and a backside surface, wherein the first memory die includes a vertical first bond wire that extends at a non-orthogonal angle from the first memory die active surface and breaches the matrix landing surface, and the subsequent memory die includes a vertical subsequent bond wire that extends from the subsequent memory die active surface and breaches the matrix landing surface;
a processor first die disposed on the first memory die and at least partially seated in the matrix, the processor first die including an active surface and a backside surface, wherein a processor bump array is disposed on the first memory die active surface, and wherein the processor bump array extends at least partially away from the matrix landing surface;
a spacer, separate from the matrix, and disposed within the matrix, the spacer disposed on the first memory die, and wherein the spacer is disposed laterally between the processor first die and the first memory die vertical first bond wire.

12. The memory module in a system in package apparatus of claim 11 , wherein the vertical first bond wire extends away from the first memory die active surface, and wherein the vertical subsequent bond wire extends at a non-orthogonal angle away from the subsequent memory die active surface.

13. The memory module in a system in package apparatus of claim 11 , wherein the vertical first bond wire extends away from the first memory die active surface, wherein the vertical subsequent bond wire extends at a non-orthogonal angle away from the subsequent memory die active surface; and wherein the vertical first bond wire and the vertical subsequent bond wire extend co-parallel from each respective first- and subsequent bond pad until each breaches the landing surface.

14. The memory module in a system in package apparatus of claim 11 , further including a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die, and a vertical second bond wire disposed on the second memory die, wherein the vertical second bond wire extends at a non-orthogonal angle from the second memory die.

15. The memory module in a system in package apparatus of claim 11 , further including:
a second memory die disposed on the first memory die active surface and between the first memory die and the subsequent memory die; and
a third memory die disposed on the second memory die active surface and between the second memory die and the subsequent memory die.

16. A computing system including a memory-die stack in a memory module in a system in package apparatus comprising a board, and mounted on the board:
a matrix including a landing surface;
a memory-die stack configured in a stair-step relationship and seated in the matrix, the memory-die stack including a first memory die and a subsequent memory die, the first memory die including an active surface and a backside surface and the subsequent memory die including an active surface and a backside surface, wherein the first memory die includes an orthogonal first bond wire that extends from the first memory die active surface and breaches the matrix landing surface, and the subsequent memory die includes an orthogonal subsequent bond wire that extends from the subsequent memory die active surface and

Assignees

• Intel Corp

Inventors

• Ding Zhicheng
• She Yong
• Liu Bin
• Tan Aiping
• Deng Li

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/50

  Bond wires · CPC title