Packages and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-2016049385-A1
Application number	US-201414460735-A
Country	US
Kind code	A1
Filing date	Aug 15, 2014
Priority date	Aug 15, 2014
Publication date	Feb 18, 2016
Grant date	—

Abstract

Packages and methods of manufacture thereof are described. In an embodiment, a package may include a first chip package and a die structure disposed over the first chip package. In an embodiment, the first chip package may include: a molding compound; a first die within the molding compound; a first via structure and a second via structure within the molding compound at opposite lateral portions of the first die, wherein the first and second via structures extend between an active surface of the first die and a first surface of the molding compound; and a second die within the molding compound, the second die disposed at the active surface of the first die and between the first via structure and the second via structure.

First claim

1 . A package comprising:
a first chip package comprising:
a molding compound;
a first die within the molding compound;
a first via structure within the molding compound at a first lateral portion of the first die, the first via structure extending between an active surface of the first die and a first surface of the molding compound;
a second via structure within the molding compound at a second lateral portion of the first die opposite the first lateral portion, the second via structure extending between the active surface of the first die and the first surface of the molding compound;
a third via structure within the molding compound laterally adjacent to and spaced apart from a first sidewall of the first die;
a fourth via structure within the molding compound laterally adjacent to and spaced apart from a second sidewall of the first die opposite the first sidewall, wherein the third via structure and the fourth via structure extend between the first surface of the molding compound and a second surface of the molding compound opposite the first surface;
a second die within the molding compound, the second die disposed at the active surface of the first die and between the first via structure and the second via structure; and
a redistribution layer (RDL) disposed over the first surface of the molding compound, wherein the RDL electrically connects the first via structure and the second via structure to the third via structure and the fourth via structure respectively; and
a die structure disposed over the first chip package.

2 . The package of claim 1 , wherein the die structure comprises at least one of an overlying chip or a second chip package.

3 . The package of claim 2 , wherein the second chip package comprises at least one of a low power double data rate die, a wide input-output memory chip, or a flash memory chip.

4 . The package of claim 1 , wherein the first chip package further comprises:
a plurality of first connectors disposed between the first chip package and the die structure, the plurality of first connectors electrically connecting the first chip package and the die structure to each other.

5 . The package of claim 1 , wherein the second die is closer to the die structure than the first die, and wherein the first surface of the molding compound faces the die structure.

6 . The package of claim 1 , wherein the second die is farther from the die structure than the first die, and wherein the first surface of the molding compound faces away from the die structure.

7 . The package of claim 1 , wherein an active surface of the second die faces the active surface of the first die.

8 . (canceled)

9 . A package comprising:
a die structure disposed over a first chip package, the first chip package comprising:
a molding compound;
at least one first via and at least one second via extending between a first surface of the molding compound and a second surface of the molding compound opposite the first surface;
a first die within the molding compound and proximate the first surface of the molding compound, the first die disposed between the at least one first via and the at least one second via;
a second die within the molding compound, the second die disposed at a first surface of the first die;
at least one third via within the molding compound laterally adjacent to and spaced apart from a first sidewall of the second die;
at least one fourth via within the molding compound laterally adjacent to and spaced apart from a second sidewall of the second die opposite the first sidewall, wherein the at least one third via and the at least one fourth via extend between the first surface of the first die and the second surface of the molding compound; and
a redistribution layer (RDL) disposed over the second surface of the molding compound, wherein the RDL electrically connects the at least one first via and the at least one second via to the at least one third via and the at least one fourth via respectively.

10 - 16 . (canceled)

17 . A package comprising:
a first chip package comprising:
a molding compound;
a first die within the molding compound;
a first via structure within the molding compound at a first lateral portion of the first die, the first via structure extending between an active surface of the first die and a first surface of the molding compound;
a second via structure within the molding compound at a second lateral portion of the first die opposite the first lateral portion, the second via structure extending between the active surface of the first die and the first surface of the molding compound;
a third via structure within the molding compound laterally adjacent to and spaced apart from a first sidewall of the first die;
a fourth via structure within the molding compound laterally adjacent to and spaced apart from a second sidewall of the first die opposite the first sidewall, wherein the third via structure and the fourth via structure extend between the first surface of the molding compound and a second surface of the molding compound opposite the first surface;
a second die within the molding compound, the second die disposed at the active surface of the first die; and
a redistribution layer (RDL) disposed over the first surface of the molding compound, wherein the RDL electrically connects the first via structure and the second via structure to the third via structure and the fourth via structure respectively; and
a die structure disposed over the first chip package.

18 - 20 . (canceled)

21 . The package of claim 1 , wherein the RDL electrically connects the first via structure and the second via structure.

22 . The package of claim 1 , wherein the RDL electrically connects the first via structure and the third via structure.

23 . The package of claim 9 , wherein the die structure comprises at least one of an overlying chip or a second chip package.

24 . The package of claim 23 , wherein the second chip package comprises at least one of a low power double data rate die, a wide input-output memory chip, or a flash memory chip.

25 . The package of claim 9 , wherein the first chip package further comprises:
a plurality of first connectors disposed between the first chip package and the die structure, the plurality of first connectors electrically connecting the first chip package and the die structure to each other.

26 . The package of claim 9 , wherein the second die is closer to the die structure than the first die, and wherein the first surface of the molding compound is directed toward the die structure.

27 . The package of claim 9 , wherein the second die is farther from the die structure than the first die, and wherein the first surface of the molding compound is directed away from the die structure.

28 . The package of claim 9 , wherein an active surface of the second die is directed toward the active surface of the first die.

29 . The package of claim 9 , wherein the RDL electrically connects the at least one first via and the at least one second via.

30 . The package of claim 9 , wherein the RDL electrically connects the at least one first via and the at least one third via.

31 . The package of claim 17 , wherein the die structure comprises at least one of an overlying chip or a second chip package.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Yee Kuo-Chung

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title