Method of fabricating transistors and stacked non-planar capacitors for memory and logic applications

Patent metadata

Field	Value
Publication number	US-12593456-B1
Application number	US-202217807667-A
Country	US
Kind code	B1
Filing date	Jun 17, 2022
Priority date	Jun 17, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

First claim

What is claimed is:

1 . A device, comprising:
a first level comprising:
a first electrode structure;
a first plate electrode on the first electrode structure;
a first plurality of plate capacitors on the first plate electrode, wherein the first plurality of plate capacitors comprises a first perovskite material;
a first signal electrode on the first plate electrode, wherein the first signal electrode is between a first pair of plate capacitors in the first plurality of plate capacitors;
a second level above the first level, the second level comprising:
a second electrode structure coupled with the first signal electrode;
a second plate electrode on the second electrode structure;
a second plurality of plate capacitors on the second plate electrode, wherein the second plurality of plate capacitors comprise a second perovskite material; and
a second signal electrode on the second plate electrode, wherein the second signal electrode is between a second pair of plate capacitors in the second plurality of plate capacitors; and
a third level above the second level, the second level comprising:
a third electrode structure coupled with the second signal electrode;
a third plate electrode on the third electrode structure; and
a third plurality of plate capacitors on the third plate electrode, wherein the third plurality of plate capacitors comprise a third perovskite material.

2 . The device of claim 1 , wherein the first plate electrode extends continuously beyond a first perimeter of individual ones of the first plurality of plate capacitors, wherein the second plate electrode extends continuously beyond a second perimeter of individual ones of the second plurality of plate capacitors, and wherein the third plate electrode extends continuously beyond a third perimeter of individual ones of the third plurality of plate capacitors.

3 . The device of claim 1 , wherein the first plate electrode, the second plate electrode and the third plate electrode are vertically aligned and have a substantially same planar surface area.

4 . The device of claim 1 , wherein the first electrode structure is laterally surrounded by a first etch stop layer, and wherein the first electrode structure comprises a first layer comprising a conductive hydrogen barrier material, and wherein the second electrode structure is laterally surrounded by a second etch stop layer, and wherein the second electrode structure comprises a second layer comprising the conductive hydrogen barrier material, and wherein the third electrode structure is laterally surrounded by a third etch stop layer, and wherein the third electrode structure comprises a third layer comprising the conductive hydrogen barrier material.

5 . The device of claim 1 , wherein individual ones of the first plurality of plate capacitors, individual ones of the second plurality of plate capacitors, and individual ones of the third plurality of plate capacitors comprise: a first electrode, a second electrode and a dielectric layer comprising a perovskite material.

6 . The device of claim 5 , further comprising: a first insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the first plurality of plate capacitors; a second insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the second plurality of plate capacitors; and a third insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the third plurality of plate capacitors.

7 . The device of claim 6 , wherein the first insulative hydrogen barrier layer is on portions of the first plate electrode, wherein the second insulative hydrogen barrier layer is on portions of the second plate electrode, and wherein the third insulative hydrogen barrier layer is on portions of the third plate electrode.

8 . The device of claim 7 , further comprising: a fourth insulative hydrogen barrier layer on the first insulative hydrogen barrier layer and on sidewalls of the first plate electrode, a fifth insulative hydrogen barrier layer on the second insulative hydrogen barrier layer and on sidewalls of the second plate electrode, and a sixth insulative hydrogen barrier layer on the third insulative hydrogen barrier layer and on sidewalls of the third plate electrode.

9 . The device of claim 8 , wherein the fourth insulative hydrogen barrier layer is adjacent to vertical portions of the first insulative hydrogen barrier layer that is adjacent to sidewalls of the individual ones of the first plurality of plate capacitors, wherein the fifth insulative hydrogen barrier layer is adjacent to vertical portions of the second insulative hydrogen barrier layer that is adjacent to sidewalls of the individual ones of the second plurality of plate capacitors, and wherein the sixth insulative hydrogen barrier layer is adjacent to vertical portions of the third insulative hydrogen barrier layer that is adjacent to sidewalls of the individual ones of the third plurality of plate capacitors.

10 . The device of claim 1 , further comprises: a first plurality of via electrodes, wherein individual ones of the first plurality of via electrodes are on a respective one of the individual ones of the first plurality of plate capacitors; a second plurality of via electrodes, wherein individual ones of the second plurality of via electrodes are on a respective one of the individual ones of the second plurality of plate capacitors; and a third plurality of via electrodes, wherein individual ones of the third plurality of via electrodes are on a respective one of the individual ones of the third plurality of plate capacitors.

11 . The device of claim 10 , further comprises: a first plurality of conductive vias, wherein individual ones of the first plurality of conductive vias are on a respective one of the individual ones of the first plurality of via electrodes and on the first signal electrode; a second plurality of conductive vias, wherein individual ones of the second plurality of conductive vias are on a respective one of the individual ones of the second plurality of via electrodes and on the second signal electrode; and a third plurality of conductive vias, wherein individual ones of the third plurality of conductive vias are on a respective one of the individual ones of the third plurality of via electrodes.

12 . The device of claim 1 , wherein the first plate electrode comprises a first thickness under individual ones of the first plurality of plate capacitors and a second thickness away from the individual ones of the first plurality of plate capacitors, wherein the second plate electrode comprises a third thickness under individual ones of the second plurality of plate capacitors and a fourth thickness away from the individual ones of the second plurality of plate capacitors, and wherein the third plate electrode comprises a fifth thickness under individual ones of the third plurality of plate capacitors and a sixth thickness away from the individual ones of the third plurality of plate capacitors.

13 . The device of claim 1 , wherein the first perovskite material, the second perovskite material and the third perovskite material comprise one of:
bismuth ferrite (BFO) or BFO with a first doping material wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table; lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanu

Assignees

• Kepler Computing Inc

Inventors

• Dokania Rajeev Kumar
• Sato Noriyuki
• Gosavi Tanay
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Rathi Somilkumar J
• Manipatruni Sasikanth

Classifications

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/33

  the capacitor extending under the transistor · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B53/20 Primary

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title