Fly bitline design for pseudo triple port memory

Patent metadata

Field	Value
Publication number	US-12588179-B2
Application number	US-202318318599-A
Country	US
Kind code	B2
Filing date	May 16, 2023
Priority date	May 16, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

First claim

What is claimed is:

1 . A memory, comprising:
a semiconductor substrate; a bitcell on the semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor; a zero metal (M 0 ) layer patterned to form a pair of local bitlines within the bitcell width, the pair of local bitlines including a local bitline coupled to a first terminal of a local data path (LDP) and including a complement local bitline coupled to a second terminal of the LDP; a first metal layer adjacent the semiconductor substrate, the first metal layer patterned to form a first pair of wordlines arranged within the bitcell height, the first pair of wordlines including a first wordline coupled to a gate of the first access transistor and including a second wordline coupled to a gate of the second access transistor; a second metal layer adjacent the M 0 layer and the first metal layer, the second metal layer patterned to form a pair of second metal layer islands within the bitcell width, the pair of second metal layer islands including a first island coupled to the first wordline and a second island coupled to the second wordline; and a third metal layer adjacent the second metal layer, the third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

2 . The memory of claim 1 , further comprising a fourth metal layer adjacent the third metal layer, the fourth metal layer patterned into a pair of fourth metal layer islands within the bitcell height, the pair of fourth metal layer islands including a first, fourth metal layer island coupled to the first interconnect and a second, fourth metal layer island coupled to the second interconnect.

3 . The memory of claim 2 , further comprising a fifth metal layer adjacent the fourth metal layer, the fifth metal layer being patterned into a pair of strapped wordlines, including a first strapped wordline coupled to the first, fourth metal layer island, and a second strapped wordline coupled to the second, fourth metal layer island.

4 . The memory of claim 3 , in which the pair of strapped wordlines comprises a first read wordline and a second read wordline.

5 . The memory of claim 3 , in which the pair of strapped wordlines comprises a first write wordline and a complement write wordline.

6 . The memory of claim 1 , in which the pair of local bitlines are coupled to a gap cell.

7 . The memory of claim 1 , further comprising a fourth metal layer in a first bitcell bank coupled to the pair of local bitlines of the bitcell in a second bitcell bank.

8 . The memory of claim 1 , further comprising a cut metal zero (CM 0 ) line separating a first bitcell bank from a second bitcell bank.

9 . The memory of claim 1 , in which the second metal layer is further patterned into a power rail between ground rails.

10 . A method for memory fabrication, the method comprising:
forming a bitcell on a semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor; patterning a zero metal (M 0 ) layer to form a pair of local bitlines within the bitcell width, the pair of local bitlines including a local bitline coupled to a first terminal of a local data path (LDP) and including a complement local bitline coupled to a second terminal of the LDP; patterning a first metal layer adjacent the semiconductor substrate to form a first pair of wordlines arranged within the bitcell height, the first pair of wordlines including a first wordline coupled to a gate of the first access transistor and including a second wordline coupled to a gate of the second access transistor; patterning a second metal layer adjacent the M 0 layer and the first metal layer to form a pair of second metal layer islands within the bitcell width, the pair of second metal layer islands including a first island coupled to the first wordline and a second island coupled to the second wordline; and patterning a third metal layer adjacent the second metal layer to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

11 . The method of claim 10 , further comprising patterning a fourth metal layer adjacent the third metal layer to form a pair of fourth metal layer islands within the bitcell height, the pair of fourth metal layer islands including a first, fourth metal layer island coupled to the first interconnect and a second, fourth metal layer island coupled to the second interconnect.

12 . The method of claim 11 , further comprising patterning a fifth metal layer adjacent the fourth metal layer to form a pair of strapped wordlines, including a first strapped wordline coupled to the first, fourth metal layer island, and a second strapped wordline coupled to the second, fourth metal layer island.

13 . The method of claim 12 , in which the pair of strapped wordlines comprises a first read wordline and a second read wordline.

14 . The method of claim 12 , in which the pair of strapped wordlines comprises a first write wordline and a complement write wordline.

15 . The method of claim 10 , in which the pair of local bitlines are coupled to a gap cell.

16 . The method of claim 10 , further comprising patterning a fourth metal layer in a first bitcell bank coupled to the pair of local bitlines of the bitcell in a second bitcell bank.

17 . The method of claim 10 , further comprising patterning a cut metal zero (CM 0 ) line separating a first bitcell bank from a second bitcell bank.

18 . The method of claim 10 , in which the second metal layer is further patterned into a power rail between ground rails.

Assignees

• Qualcomm Inc

Inventors

• Sharma Sunil
• Pallerla Arun Babu
• Son Sung

Classifications

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title