Two-port SRAM connection structure

Patent metadata

Field	Value
Publication number	US-9672903-B2
Application number	US-201615253365-A
Country	US
Kind code	B2
Filing date	Aug 31, 2016
Priority date	Mar 11, 2013
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.

First claim

What is claimed is:

1. A static random access memory (SRAM) device comprising:
a peripheral logic circuit;
a plurality of two-port SRAM cells, each two-port SRAM cell comprising:
a write port portion including a first plurality of transistors; and
a read port portion including a second plurality of transistors;

a first plurality of metal lines including a write bit line, an inverse write bit line, a read bit line, a write word line landing pad, and a read word line landing pad, wherein the first plurality of metal lines is located in a first metal layer;
a second plurality of metal lines including a write word line, wherein the second plurality of metal lines is located in a second metal layer;
a third plurality of metal lines including a global write bit line and an inverse global write bit line, wherein the third plurality of metal lines is located in a third metal layer; and
a plurality of jumper structures, each jumper structure comprising:
a first metal landing pad located in the second metal layer and electrically connected to the write bit line and to the global write bit line;
a second metal landing pad located in the second metal layer and electrically connected to the inverse write bit line and the inverse global write bit line; and
a third metal landing pad located in the second metal layer and electrically connected to the read bit line and a peripheral metal line of the peripheral logic circuit, the peripheral metal line located in the first metal layer.

2. The SRAM device of claim 1 , wherein:
the peripheral logic circuit includes parallel metal lines with a first pitch, and
each of the first, second and third metal landing pads has a width greater than 2 times the first pitch.

3. The SRAM device of claim 1 , wherein:
the plurality of two-port SRAM cells are arranged into a plurality of columns and a plurality of rows, thereby forming a two-port SRAM array,
the write bit line, inverse write bit line, read bit line, global write bit line, and inverse global write bit line are laid out in a direction that is parallel to a direction of the plurality of columns, and
each of the plurality of columns includes at least one jumper structure.

4. The SRAM device of claim 3 , wherein the plurality of jumper structures includes first jumper structures that extend across a first edge of the array and second jumper structures that extend across a second edge of the array that opposes the first edge of the array.

5. The SRAM device of claim 3 , wherein the plurality of jumper structures includes first jumper structures that extend across a first edge of the array.

6. The SRAM device of claim 1 , wherein:
the write bit line, the inverse write bit line, the global write bit line, the inverse global write bit line, and the read bit line are routed in a first routing direction,
the write word line is routed in a second routing direction,
the first routing direction is perpendicular to the second routing direction, and
the global write bit line has a width that is at least 1.2 times a width of the write bit line.

7. The SRAM device of claim 1 , wherein:
the first plurality of transistors includes first and second pull up devices and first and second pull down devices configured as a pair of cross-coupled inverters,
the second plurality of transistors includes a third pull down device,
the first plurality of metal lines further includes a first return voltage line, a second return voltage line, and a supply voltage line,
the first return voltage line is electrically connected to a source terminal of the first pull down device,
the second return voltage line is electrically connected to source terminals of the second and third pull down devices, and
the supply voltage line is electrically connected to source terminals of the first and second pull up devices.

8. The SRAM device of claim 1 , wherein:
the second plurality of transistors includes a third pass-gate device, and
the second plurality of metal lines located in the second metal layer further comprises a read word line connected to a gate terminal of the third pass-gate device.

9. The SRAM device of claim 1 , wherein:
the second plurality of transistors includes a third pass-gate device, and
each two-port SRAM cell further comprises a read word line connected to a gate terminal of the third pass-gate device, the read word line located in a fourth metal layer and being routed in a same direction as the write word line, the read word line having a width that is at least 1.5 times a width of the write word line.

10. A static random access memory (SRAM) device comprising:
a peripheral logic circuit;
a first sub array and a second sub array, the first and second sub arrays each comprising:
a plurality of two-port SRAM cells, each two-port SRAM cell comprising:
a write port portion including a first plurality of transistors; and
a read port portion including a second plurality of transistors;

a first plurality of metal lines including a write bit line, an inverse write bit line, a read bit line, a write word line landing pad, and a read word line landing pad, wherein the first plurality of metal lines is located in a first metal layer;
a second plurality of metal lines including a write word line, wherein the second plurality of metal lines is located in a second metal layer; and
a third plurality of metal lines including a global write bit line and an inverse global write bit line, wherein the third plurality of metal lines is located in a third metal layer;
wherein the write bit line, the inverse write bit line, the global write bit line, and the inverse global write bit line each have a routing length across the first and second sub arrays, and
wherein the read bit line of the first sub array and the read bit line of the second sub array are physically isolated; and
a plurality of jumper structures, each jumper structure comprising:
a first metal landing pad located in the second metal layer and electrically connected to the write bit line and to the global write bit line;
a second metal landing pad located in the second metal layer and electrically connected to the inverse write bit line and the inverse global write bit line; and
a third metal landing pad located in the second metal layer and electrically connected to the read bit line and a peripheral metal line of the peripheral logic circuit, the peripheral metal line located in the first metal layer.

11. The SRAM device of claim 10 , further comprising a global read bit line located in a third metal layer.

12. The SRAM device of claim 10 , wherein the read bit line and the peripheral metal line extend parallel to each other and do not overlap.

13. The SRAM device of claim 10 , wherein:
the plurality of two-port SRAM cells are arranged into a plurality of columns and a plurality of rows, thereby forming a two-port SRAM array,
the write bit line, inverse write bit line, read bit line, global write bit line, and inverse global write bit line are laid out in a direction that is parallel to a direction of the plurality of columns, and
each of the plurality of columns includes at least one jumper structure.

14. The SRAM device of claim 10 , wherein:
the write bit line, the inverse write bit line, the global write bit line, the inverse global write bit line, and the read bit line are routed in a first routing direction,
the write word line is routed in a second routing direction,
the first routing direction is perpendicular to the second routing direction, and
the global write bit line has a width that is at least 1.2 times a width of the write bit line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semicondutor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• B81C1/00253

  Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246 · CPC title