Memory device including a word line with portions with different sizes in different metal layers

Patent metadata

Field	Value
Publication number	US-11404113-B2
Application number	US-202017035118-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Jun 18, 2020
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

First claim

What is claimed is:

1. A memory device, comprising:
a first word line configured to transmit a first word line signal to a first set of memory cells, wherein a first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer; and
a second word line configured to transmit a second word line signal to a second set of memory cells, wherein a first portion of the second word line is formed in the first metal layer, a second portion of the second word line is formed in the second metal layer, and a third portion of the second word line is formed in a third metal layer above the second metal layer,
wherein the first portion and the second portion of the first word line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second word line have sizes that are different from each other,
wherein the third portion of the second word line is partially overlapped with the second portion of the first word line, in a layout view,
wherein the second portion of the second word line comprises a plurality of segments that are separated from each other.

2. The memory device of claim 1 , wherein the third portion of the second word line is partially overlapped with the second portion of the second word line, in the layout view.

3. The memory device of claim 2 , wherein at least one part of the second portion of the first word line is disposed between two of the plurality of segments, in the layout view.

4. The memory device of claim 1 , wherein at least one part of the second portion of the first word line is disposed between two of the plurality of segments, in the layout view.

5. The memory device of claim 1 , wherein
a third portion of the first word line is formed in a fourth metal layer, and
the first portion, the second portion and the third portion of the first word line have widths that are different from each other.

6. The memory device of claim 5 , wherein in the layout view,
the third portion of the first word line is directly overlapped with the second portion of the first word line.

7. The memory device of claim 5 , wherein the fourth metal layer is between the first metal layer and the second metal layer.

8. The memory device of claim 1 , wherein a width of the second portion of the second word line is smaller than a width of the second portion of the first word line, and is smaller than a width of the third portion of the second word line.

9. A memory device, comprising:
a first word line configured to transmit a first word line signal to a first set of memory cells arranged in a first row, wherein a first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer;
a second word line configured to transmit a second word line signal to a second set of memory cells arranged in a second row, wherein a first portion of the second word line is formed in the first metal layer, a second portion of the second word line is formed in the second metal layer, and a third portion of the second word line is formed in a third metal layer above the second metal layer;
a third word line configured to transmit a third word line signal to a third set of memory cells arranged in a third row, wherein a first portion of the third word line is formed in the first metal layer, and a second portion of the third word line is formed in the second metal layer; and
a fourth word line configured to transmit a fourth word line signal to a fourth set of memory cells arranged in a fourth row, wherein a first portion of the fourth word line is formed in the first metal layer, a second portion of the fourth word line is formed in the second metal layer, and a third portion of the fourth word line is formed in the third metal layer,
wherein a third portion of the first word line is formed in a fourth metal layer and the third portion of the first word line is directly overlapped with the second portion of the first word line, in a layout view,
wherein the second portion of the second word line comprises a plurality of segments that are separated from each other.

10. The memory device of claim 9 , wherein
the third portion of the second word line is partially overlapped with the second portion of the first word line, in the layout view.

11. The memory device of claim 9 , wherein an amount of the plurality of segments is substantially equal to or greater than an amount of the first set of memory cells or the second set of memory cells arranged in a column and the first row or the second row.

12. The memory device of claim 9 , wherein
the second portion of the first word line and the second portion of the second word line extend in a first direction, and
a protruding part of the second portion of the first word line extends in a second direction, and disposed between two of the plurality of segments, in the layout view.

13. The memory device of claim 12 , wherein in the layout view, the protruding part of the second portion of the first word line, the plurality of segments, and the third portion of the second word line are partially overlapped together.

14. The memory device of claim 9 , wherein
the first portion and the second portion of the first word line have sizes that are different from each other,
the first portion, the second portion and the third portion of the second word line have sizes that are different from each other,
the first portion and the second portion of the third word line have sizes that are different from each other,
the first portion, the second portion and the third portion of the fourth word line have sizes that are different from each other,
sizes of the second portion of the first word line and the second portion of the third word line are substantially the same, and are different from sizes of the second portion of the second word line and the second portion of the fourth word line that are substantially the same, and
the first word line, the second word line, the third word line, and the fourth word line have equivalent resistances that are substantially the same.

15. The memory device of claim 9 , wherein
fourth portions of the second word line are formed in a fifth metal layer between the second metal layer and the third metal layer,
the fourth portions of the second word line are partially overlapped with the second portion of the first word line, the second portion of the second word line, and the third portion of the second word line, in the layout view.

16. The memory device of claim 15 , wherein the fourth portions of the second word line comprises a plurality of segments that are separated from each other.

17. The memory device of claim 16 , wherein fifth portions of the second word line are formed in the fourth metal layer between the first metal layer and the second metal layer.

18. A memory device, comprising:
a first portion of a first word line and a first portion of a second word line formed in a first metal layer;
a second portion of the first word line and a second portion of the second word line formed in a second metal layer above the first metal layer;
third portions of the second word line formed in a third metal layer between the second metal layer and a fourth metal layer that is above the second metal layer; and
a fourth portion of the second word line formed in the fourth metal layer,
wherein the first portion and the second p

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nien Yi-Hsin
• Zhao Wei-Chang
• Lin Chih-Yu
• Fujiwara Hidehiro
• Chen Yen-Huei
• Wang Ru-Yu

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title