Fly bitline design for pseudo triple port memory
US-12588179-B2 · Mar 24, 2026 · US
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Sharma Sunil patents
Sharma Sunil is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sharma Sunil |
| Total patents | 21 |
| First publication | Feb 28, 2019 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory with hardware for verification of layout
US-2026050731-A1 · Feb 19, 2026 · US
Memory with one-transistor-based bit line tracking circuit
US-12555622-B2 · Feb 17, 2026 · US
Systems, apparatuses, methods, and computer program products for generating an aviation operations package
US-2026005851-A1 · Jan 1, 2026 · US
Memory with bitcell-to-periphery interface tap cell
US-2025374511-A1 · Dec 4, 2025 · US
Reducing current-resistor (ir) drops using feol and meol structures
US-2025132255-A1 · Apr 24, 2025 · US
Memory with One-Transistor-Based Bit Line Tracking Circuit
US-2025037753-A1 · Jan 30, 2025 · US
Method and system for recommending tool configurations in machining
US-12165083-B2 · Dec 10, 2024 · US
Fly bitline design for pseudo triple port memory
US-2024389292-A1 · Nov 21, 2024 · US
Automated self-healing of a computing process
US-11797877-B2 · Oct 24, 2023 · US
Recent patents
Latest publications not already listed above.
Static random-access memory (SRAM) array circuits including bilateral well tap cells with reduced width folded finger structure
US-11469239-B1 · Oct 11, 2022 · US
Static random-access memory (sram) array circuits including bilateral well tap cells with reduced width folded finger structure
US-2022320114-A1 · Oct 6, 2022 · US
Memory
US-11424250-B2 · Aug 23, 2022 · US
Static random access memory (sram) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and sram bit cell array circuits
US-2022102360-A1 · Mar 31, 2022 · US
Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits
US-11289495-B1 · Mar 29, 2022 · US
Memory
US-2022068940-A1 · Mar 3, 2022 · US
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods
US-11251123-B1 · Feb 15, 2022 · US
System and method for allocating vehicles in ride-sharing systems
US-11195245-B2 · Dec 7, 2021 · US
Method and system for recommending tool configurations in machining
US-2021216896-A1 · Jul 15, 2021 · US
System and method for allocating vehicles in ride-sharing systems
US-2019206010-A1 · Jul 4, 2019 · US
Automated self-healing of a computing process
US-2019065990-A1 · Feb 28, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 14 |
| Tata Consultancy Services Ltd | 2 |
| Accenture Global Solutions Ltd | 2 |
| Ani Tech Private Ltd | 2 |
| Honeywell Int Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B10/12 | 10 |
| H10D89/10 | 8 |
| H01L27/1104 | 7 |
| H10B10/18 | 6 |
| G11C11/419 | 5 |