Package architecture for quasi-monolithic chip with backside power

Patent metadata

Field	Value
Publication number	US-12581938-B2
Application number	US-202217820961-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects, wherein an end layer in the plurality of layers is proximate to a first side of the plurality of layers; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects having a pitch of less than 10 micrometers between adjacent second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side, wherein:
the end layer comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer,
the conductive traces in the support structure are coupled by the second interconnects to the TDV in the end layer, and
the conductive traces in the support structure are conductively coupled to a power circuit.

2 . The microelectronic assembly of claim 1 , wherein:
the end layer is a first end layer, and IC dies in a second end layer proximate to the second side of the plurality of layers comprises through-substrate vias (TSVs).

3 . The microelectronic assembly of claim 1 , further comprising:
a first type of conductive traces; and a second type of conductive traces, wherein:
the first type of conductive traces is larger than the second type of conductive traces,
the first type of conductive traces is configured to carry power and is conductively coupled to the power circuit, and
the second type of conductive traces is configured to conduct electrical signals and is not conductively coupled to the power circuit.

4 . The microelectronic assembly of claim 3 , wherein:
the IC dies comprise respective substrates attached to respective metallization stacks, and the respective metallization stacks include the dielectric material, the first type of conductive traces, and the second type of conductive traces.

5 . The microelectronic assembly of claim 4 , wherein:
the respective metallization stack in at least one IC die in the end layer is on one side of the respective substrate, the first type of conductive traces and the second type of conductive traces are in correspondingly separate layers within the respective metallization stack, the at least one IC die in the end layer comprises TSVs in the respective substrate, each TSV has a first end proximate to the first interconnects, and a second end distant from the first interconnects, the second end being proximate to the one side of the respective substrate, the first end is coupled to the conductive traces in the support structure by the first interconnects, and the second end is coupled to the first type of conductive traces in the respective metallization stack of the at least one IC die.

6 . The microelectronic assembly of claim 4 , wherein:
at least one IC die in the end layer comprises a first metallization stack on one side of the respective substrate and a second metallization stack on an opposing side of the respective substrate, the first type of conductive traces is in the first metallization stack, and the second type of conductive traces is in the second metallization stack, and the first type of conductive traces is coupled to the conductive traces in the support structure by the first interconnects.

7 . The microelectronic assembly of claim 1 , further comprising a plurality of TDVs in the end layer.

8 . The microelectronic assembly of claim 7 , wherein the TDVs are trench vias arranged in rows between the IC dies in the end layer.

9 . A microelectronic assembly, comprising:
a package substrate; a first IC die coupled to the package substrate; a second IC die coupled to the first IC die, the second IC die being surrounded by a dielectric material; and a support structure coupled to the second IC die on a side of the second IC die opposite to the first IC die, the support structure comprising a power plane configured to be conductively coupled to one or more power sources, wherein: the first IC die is coupled to the power plane of the support structure by through-dielectric vias (TDVs) in the dielectric material surrounding the second IC die, and the second IC die is coupled to the power plane of the support structure by first-level interconnects (FLIs) having a pitch of less than 10 micrometers between adjacent interconnects.

10 . The microelectronic assembly of claim 9 , wherein the first IC die and the second IC die are coupled by FLIs having a pitch of less than 10 micrometers between adjacent interconnects.

11 . The microelectronic assembly of claim 9 , the second IC die comprises through-substrate vias (TSVs) conductively coupled to the first-level interconnects with the power plane of the support structure.

12 . The microelectronic assembly of claim 9 , wherein
the FLIs are conductively coupled to first conductive traces in the second IC die, the second IC die comprises second conductive traces, and the first conductive traces are thicker than the second conductive traces.

13 . The microelectronic assembly of claim 12 , wherein:
the first conductive traces are in a first metallization stack, the second conductive traces are in a second metallization stack, and the first metallization stack is separated from the second metallization stack by a substrate.

14 . The microelectronic assembly of claim 9 , wherein the dielectric material comprises a compound of silicon and at least one of oxygen, nitrogen and carbon.

15 . The microelectronic assembly of claim 9 , wherein the support structure is a silicon wafer.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Liff Shawna M
• Mallik Debendra
• Pelto Christopher M
• Jun Kimin
• Swan Johanna M
• Jiang Lei
• Eid Feras
• Valavala Krishna Vasanth
• Braunisch Henning
• Morrow Patrick
• Lambert William J

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title