Nanowire transistors and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12568643-B2
Application number	US-202016914145-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first transistor structure, comprising:
a stack of a plurality of first channel structures, wherein each of the first channel structures comprises silicon, wherein the first channel structures each comprise a first section decreasing in thickness from a first thickness to a second thickness along a longitudinal direction, and a second section increasing in thickness from the second thickness to the first thickness along the longitudinal direction, wherein the second thickness in adjacent ones of the first channel structures have a first vertical separation therebetween, and wherein the first thickness in adjacent ones of the first channel structures have a second vertical separation therebetween, smaller than the first vertical separation;
a source material and a drain material coupled to opposite ends of the first channel structures;
a gate electrode material between the source material and the drain material, and within the first vertical separation; and
a first thickness of gate dielectric material within the first vertical separation and between the gate electrode material and each of the first channel structures; and
a second transistor structure, comprising:
a stack of a plurality of second channel structures with the second vertical separation, wherein each of the second channel structures comprises silicon and wherein the second channel structures have substantially the first thickness in an absence of the first and second sections;
a source material and a drain material coupled to opposite ends of the second channel structures;
a gate electrode material between the source material and the drain material within the second vertical separation; and
a second thickness of gate dielectric material within the second vertical separation and between the gate electrode material and each of the second channel structures, wherein the second thickness of gate dielectric material is less than the first thickness of gate dielectric material, and wherein:
the first thickness of gate dielectric material comprises a first dielectric material layer in contact with the first channel structures and a third dielectric material layer in contact with the first dielectric material layer; the second thickness of gate dielectric material comprises a second dielectric material layer in contact with the first channel structures and a fourth dielectric material layer in contact with the second dielectric material layer, the fourth dielectric material layer having substantially the same composition and substantially the same thickness as the third dielectric material layer; and the first dielectric material layer and the second dielectric material layer have substantially the same composition.

2 . The apparatus of claim 1 , wherein the first dielectric material layer and the second dielectric material layer both comprise silicon and oxygen.

3 . The apparatus of claim 1 , wherein the first dielectric material layer is thicker than the second dielectric material layer.

4 . The apparatus of claim 3 , wherein the first dielectric material layer has a thickness over 1.5 nm and the second dielectric material layer has a thickness less than 1 nm.

5 . The apparatus of claim 1 , wherein the third dielectric material layer and the fourth dielectric material layer both comprise a metal and oxygen.

6 . The apparatus of claim 1 , wherein:
the first vertical separation is between a lowermost surface of an upper one of the first channel structures and an uppermost surface of a lower one of the first channel structures; the second vertical separation is between an upper one of the second channel structures and an uppermost surface of a lower one of the second channel structures; and the second vertical separation is at least 7 nm.

7 . The apparatus of claim 1 , wherein the first channel structures each comprise a bridge section between the first and the second sections, the bridge section having substantially the second thickness.

8 . An apparatus, comprising:
a first transistor structure, comprising:
a stack of a plurality of first channel structures, wherein each of the first channel structures comprises silicon and has a first section decreasing in thickness from a first thickness to a second thickness along a longitudinal direction, and a second section increasing in thickness from the second thickness to the first thickness along the longitudinal direction;
a source material and a drain material coupled to opposite ends of the first channel structures;
a gate electrode material between the source material and the drain material; and
a first thickness of gate dielectric material between the gate electrode material and each of the first channel structures; and
a second transistor structure, comprising:
a stack of a plurality of second channel structures, wherein each of the second channel structures comprises silicon, and lacks the first and second sections;
a source material and a drain material coupled to opposite ends of the second channel structures;
a gate electrode material between the source material and the drain material;
a second thickness of gate dielectric material between the gate electrode material and each of the second channel structures, wherein the second thickness of gate dielectric material is less than the first thickness of gate dielectric material, and wherein:
the first thickness of gate dielectric material comprises a first dielectric material layer in contact with the first channel structures;
the second thickness of gate dielectric material comprises a second dielectric material layer in contact with the second channel structures;
the first thickness of gate dielectric material comprises a third dielectric material layer in contact with the first dielectric material layer;
the second thickness of gate dielectric material comprises a fourth dielectric material layer in contact with the second dielectric material layer;
the third dielectric material layer and the fourth dielectric material layer comprises a metal and oxygen; and
the third dielectric material layer has substantially the same thickness as the fourth dielectric material layer.

9 . The apparatus of claim 8 , wherein the second channel structures have substantially the first thickness over an entire distance between the source material and the drain material.

10 . The apparatus of claim 8 , wherein:
the first dielectric material layer and the second dielectric material layer have substantially the same composition.

11 . The apparatus of claim 10 , wherein the first dielectric material layer and the second dielectric material layer both comprise silicon and oxygen.

12 . The apparatus of claim 10 , wherein the first dielectric material layer is thicker than the second dielectric material layer.

13 . The apparatus of claim 10 , wherein the third dielectric material layer and the fourth dielectric material layer have substantially the same composition.

14 . The apparatus of claim 8 , wherein a first vertical separation between a lowermost surface of an upper one of the first channel structures and an uppermost surface of a lower one of the first channel structures is greater than a second vertical separation between an upper one of the second channel structures and an uppermost surface of a lower one of the second channel structures.

Assignees

• Intel Corp

Inventors

• Guha Biswajeet
• Greene Brian
• Chao Robin
• Faust Adam
• Lin Chung-Hsun
• Tsai Curtis
• Fischer Kevin

Classifications

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title