Nanosheet transistors having different gate dielectric thicknesses on the same chip

Patent metadata

Field	Value
Publication number	US-2018197784-A1
Application number	US-201715846447-A
Country	US
Kind code	A1
Filing date	Dec 19, 2017
Priority date	Jan 12, 2017
Publication date	Jul 12, 2018
Grant date	—

Abstract

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

First claim

What is claimed is:

1 . A method for forming a semiconductor device, the method comprising:
forming a first sacrificial layer between a first nanosheet and a second nanosheet; forming a second sacrificial layer between a third nanosheet and a fourth nanosheet; doping the first nanosheet; and concurrently removing the first sacrificial layer, the first nanosheet, and the second sacrificial layer.

2 . The method of claim 1 further comprising forming a dielectric layer over a channel region of the first and second nanosheets.

3 . The method of claim 2 further comprising forming a first gate over the dielectric layer.

4 . The method of claim 3 further comprising forming a first gate contact on the first gate.

5 . The method of claim 3 further comprising forming a second gate over a channel region of the third and fourth nanosheets.

6 . The method of claim 5 further comprising forming a second gate contact on the second gate.

7 . The method of claim 1 , wherein the first and second nanosheets are vertically stacked nanosheets in a first nanosheet stack and the third and fourth nanosheets are vertically stacked nanosheets in a second nanosheet stack.

8 . The method of claim 7 , wherein each of the nano sheets in the first and second nanosheet stacks is separated by a sacrificial layer.

9 . The method of claim 7 , wherein each of the nano sheets in the first and second nanosheet stacks comprises a thickness of about 4 nm to about 10 nm.

10 . The method of claim 4 , wherein a thickness of the first sacrificial layer is at least twice a thickness of the second sacrificial layer.

11 . The method of claim 7 , wherein the first and second nanosheet stacks are concurrently formed by removing portions of a semiconductor layer.

12 . The method of claim 1 , wherein the nanosheets comprise silicon and the sacrificial layers comprise silicon germanium.

13 . The method of claim 1 , wherein doping the first nanosheet comprises plasma doping the first nanosheet with a germanium dopant at a temperature of about 400 degrees Celsius to about 700 degrees Celsius.

14 . A method for forming a semiconductor device, the method comprising:
forming a sacrificial layer between a first nanosheet and a second nanosheet; doping the first nanosheet; and concurrently removing the first nanosheet and the sacrificial layer.

15 . The method of claim 14 further comprising:
forming a gate over a channel region of the first and second nanosheets; and
forming a gate contact on the gate.

16 . The method of claim 14 , wherein the first and second nanosheets are vertically stacked nanosheets in a nanosheet stack.

17 . The method of claim 16 , wherein the nanosheet stack further comprises a plurality of nanosheets alternating with a plurality of sacrificial layers such that each pair of adjacent nanosheets is separated by a sacrificial layer.

18 . The method of claim 16 , wherein each nanosheet of the nanosheet stack comprises a thickness of about 4 nm to about 10 nm.

19 . The method of claim 14 , wherein the first and second nanosheets comprise silicon nanosheets and the sacrificial layer comprises silicon germanium.

20 . The method of claim 14 , wherein doping the first nanosheet comprises plasma doping the first nanosheet with a germanium dopant at a temperature of about 400 degrees Celsius to about 700 degrees Celsius.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/0673

  Electricity · mapped topic

• H01L21/2236

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic