Anti-fuse bit cell with dual gate dielectrics
US-2026096095-A1 · Apr 2, 2026 · US
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Chao Robin patents
Chao Robin is listed as an inventor on 67 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chao Robin |
| Total patents | 67 |
| First publication | Feb 14, 2019 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Complementary gate cut plugs for strain optimization
US-2026090024-A1 · Mar 26, 2026 · US
Gate-all-around integrated circuit structures having differentiated release layers
US-2026090025-A1 · Mar 26, 2026 · US
Defect-free epitaxial source and drain structures for ribbon field effect transistors
US-2026090023-A1 · Mar 26, 2026 · US
Improved removal of sacrificial material for minimized channel extensions
US-2026090039-A1 · Mar 26, 2026 · US
Nanowire transistors and methods of fabrication
US-12568643-B2 · Mar 3, 2026 · US
Backside contact structure with enhanced ohmic contact
US-2026032960-A1 · Jan 29, 2026 · US
Gate-all-around integrated circuit structures having differentiated internal spacers
US-2026006871-A1 · Jan 1, 2026 · US
Integrated circuit structure with zero diffusion break and wrap-around contact
US-2026006837-A1 · Jan 1, 2026 · US
Strain engineering using gate cuts
US-2026006859-A1 · Jan 1, 2026 · US
Recent patents
Latest publications not already listed above.
Self-aligned fork-last backbone for forksheet transistors
US-2026006842-A1 · Jan 1, 2026 · US
Silicon source and drain trench fill for wider contacts
US-2026006906-A1 · Jan 1, 2026 · US
Integrated circuit structures having stress-inducing gate cut plugs
US-2026006860-A1 · Jan 1, 2026 · US
Sacrificial ribbon for uniform workfunction and capacitance benefits
US-2026006846-A1 · Jan 1, 2026 · US
Transistor metallization endcap scaling for performance optimization
US-2026006833-A1 · Jan 1, 2026 · US
Backside etch processes for ultra uniformity of front-end structures
US-2026005067-A1 · Jan 1, 2026 · US
Fabrication of ribbon cfets with optimized nmos and pmos channel materials
US-2026006873-A1 · Jan 1, 2026 · US
Fabrication of gate-all-around integrated circuit structures having selectively grown metal gate structures
US-2026006838-A1 · Jan 1, 2026 · US
Integrated circuit structures having differentiated dielectric boundary walls
US-2026006836-A1 · Jan 1, 2026 · US
Integrated circuit structures having hybrid channel layout
US-2025393250-A1 · Dec 25, 2025 · US
Contact over active gate structures with widened and lower capacitance insulating cap layers for advanced integrated circuit structure fabrication
US-2025386578-A1 · Dec 18, 2025 · US
Integrated circuit structures with backside isolation structure
US-2025386580-A1 · Dec 18, 2025 · US
Dipole threshold voltage tuning for high voltage transistor stacks
US-12471354-B2 · Nov 11, 2025 · US
Nanoribbon-based transistors with etch stop layer to assist subfin removal
US-2025324690-A1 · Oct 16, 2025 · US
Integrated circuit structure with deep via bar width tuning
US-2025323127-A1 · Oct 16, 2025 · US
Zero diffusion break for improving transistor density
US-2025311273-A1 · Oct 2, 2025 · US
Backside-patterned fin isolation structures between semiconductor devices
US-2025311404-A1 · Oct 2, 2025 · US
Ribbon complementary fet (cfet) metal gate multi-voltage threshold integration
US-2025311428-A1 · Oct 2, 2025 · US
Dielectric wall used to separate gate dielectric between adjacent devices
US-2025311353-A1 · Oct 2, 2025 · US
Backside gate cut formation
US-2025311363-A1 · Oct 2, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 65 |
| Commissariat Energie Atomique | 2 |
| IBM | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/6735 | 50 |
| H10D84/038 | 49 |
| H10D62/121 | 48 |
| H10D30/6757 | 45 |
| H10D30/43 | 41 |