Semiconductor device including a field effect transistor and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12563827-B2
Application number	US-202418744905-A
Country	US
Kind code	B2
Filing date	Jun 17, 2024
Priority date	Feb 10, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first active pattern and a second active pattern respectively on a PMOSFET region and an NMOSFET region of a substrate; a first channel pattern on the first active pattern, the first channel pattern including a plurality of first semiconductor patterns that are stacked and spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate; a second channel pattern on the second active pattern, the second channel pattern including a plurality of second semiconductor patterns that are stacked and spaced apart from each other in the vertical direction; and a gate electrode on the first and second channel patterns, the gate electrode extending lengthwise in a first direction parallel to the top surface of the substrate, wherein the gate electrode includes:
inner gate electrodes that fill an inner area between first semiconductor patterns of the plurality of first semiconductor patterns that are adjacent to each other and between second semiconductor patterns of the plurality of second semiconductor patterns that are adjacent to each other; and
an outer gate electrode that fills an outer area outside the plurality of first semiconductor patterns and the plurality of second semiconductor patterns,
wherein the outer gate electrode includes:
a first metal pattern that covers opposite sidewalls of the inner gate electrodes; and
a second metal pattern on the first metal pattern, and
wherein a thickness of the second metal pattern on the PMOSFET region is different from a thickness of the second metal pattern on the NMOSFET region.

2 . The semiconductor device of claim 1 , wherein a thickness of the first metal pattern on the PMOSFET region is different from a thickness of the first metal pattern on the NMOSFET region.

3 . The semiconductor device of claim 1 ,
wherein the first metal pattern includes metal nitride, wherein the second metal pattern includes one selected from metal carbide and metal nitride, and wherein each of the metal carbide and the metal nitride is doped with at least one selected from silicon and aluminum.

4 . The semiconductor device of claim 3 , wherein a concentration of the silicon or the aluminum in the second metal pattern ranges from about 0.1 at % to about 25 at %.

5 . The semiconductor device of claim 1 , further comprising:
a fill metal pattern on the second metal pattern, wherein a resistance of the fill metal pattern is less than a resistance of the second metal pattern.

6 . The semiconductor device of claim 1 ,
wherein a component of the first metal pattern on the PMOSFET region is substantially the same as a component of the first metal pattern on the NMOSFET region, and wherein a component of the second metal pattern on the PMOSFET region is substantially the same as a component of the second metal pattern on the NMOSFET region.

7 . The semiconductor device of claim 1 ,
wherein the inner gate electrodes include:
a first inner gate electrode on the PMOSFET region, and
a second inner gate electrode on the NMOSFET region,
wherein each of the first and second inner gate electrodes includes aluminum containing titanium nitride, and wherein an aluminum concentration in the first inner gate electrode is different from an aluminum concentration in the second inner gate electrode.

8 . The semiconductor device of claim 1 ,
wherein an uppermost one of the inner gate electrodes is on a bottom surface of an uppermost one of the plurality of first semiconductor patterns and on a bottom surface of an uppermost one of the plurality of second semiconductor patterns, and wherein the uppermost one of the inner gate electrodes includes an impurity derived from the outer gate electrode.

9 . The semiconductor device of claim 1 , further comprising:
a gate dielectric layer on the first and second channel patterns, wherein the gate dielectric layer is between the plurality of first semiconductor patterns and the inner gate electrodes, between the plurality of second semiconductor patterns and the inner gate electrodes, between the plurality of first semiconductor patterns and the outer gate electrode, and between the plurality of second semiconductor patterns and the outer gate electrode.

10 . A semiconductor device, comprising:
a first active pattern on an NMOSFET region of a substrate; a second act on a PMOSFET region of the substrate; a first channel pattern on the first active pattern, the first channel pattern including a plurality of first semiconductor patterns that are stacked and spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate; a second channel pattern on the second active pattern, the second channel pattern including a plurality of second semiconductor patterns that are stacked and spaced apart from each other in the vertical direction; and a gate electrode on the first channel pattern, the gate electrode extending lengthwise in a first direction parallel to the top surface of the substrate, wherein the gate electrode includes:
a first metal pattern; and
a second metal pattern on the first metal pattern, and
wherein the first metal pattern surrounds each of the plurality of first semiconductor patterns, wherein the gate electrode includes inner gate electrodes on the PMOSFET region, wherein the inner gate electrodes fill a second inner area between second semiconductor patterns of the plurality of second semiconductor patterns that are adjacent to each other, wherein the first metal pattern covers opposite sidewalls of each of the inner gate electrodes, and wherein a thickness of the second patterns on the PMOSFET region is different from a thickness of the second metal pattern on the NMOSFET region.

11 . The semiconductor device of claim 10 ,
wherein the first metal pattern fills a first inner area between first semiconductor patterns of the plurality of first semiconductor patterns that are adjacent to each other, and wherein the second metal pattern fills a remaining portion of the first inner area that the first metal pattern fills.

12 . The semiconductor device of claim 10 ,
wherein the first metal pattern includes a metal nitride, wherein the second metal pattern includes a metal carbide a metal nitride, and wherein each of the metal carbide and the metal nitride is doped with at least one selected from silicon and aluminum.

13 . The semiconductor device of claim 10 , wherein a thickness of the first metal pattern on the PMOSFET region is different from a thickness of the first metal pattern on the NMOSFET region.

14 . A semiconductor device, comprising:
a first active pattern and a second active pattern respectively on a PMOSFET region and an NMOSFET region of a substrate; a device isolation layer that fills a trench between the first and second active patterns; a first fin structure on the first active pattern, the first fin structure including a plurality of first inner gate electrodes and a plurality of first semiconductor patterns that are alternately stacked on the first active pattern; a second fin structure on the second active pattern, the second fin structure including a plurality of second inner gate electrodes and a plurality of second semiconductor patterns that are alternately stacked on the second active pattern; a gate dielectric layer that surrounds each of the plurality of first semiconductor patterns and the plurality of second semiconductor patterns; an outer gate electrode that covers the first and second fin structures and extends lengthwise in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Inhyun
• Yang Junggil
• Kim Minju

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0179

  the gate conductors having different shapes or dimensions · CPC title