Semiconductor device and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-2020105758-A1
Application number	US-201816147027-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first transistor formed in a first region of the semiconductor device, the first transistor comprising:
a first channel structure extending between a source terminal and a drain terminal of the first transistor;
a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device; and
a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure, the first metal cap having a different work function from another portion of the first gate structure.

2 . The semiconductor device of claim 1 , wherein
the first metal cap is configured to have a smaller dimension than the first channel structure in a channel width cross-section.

3 . The semiconductor device of claim 1 , wherein the first gate structure further comprises a first metal layer that has a different work function from the first metal cap.

4 . The semiconductor device of claim 1 , further comprising:
a second transistor formed in a second region of the semiconductor device, the second transistor comprising:
a third channel structure extending between a source terminal and a drain terminal of the second transistor;
a fourth channel structure that is stacked on the third channel structure in the vertical direction above the substrate; and
a second gate structure configured to wrap around the third channel structure and the fourth channel structure with a second metal cap between the third channel structure and the fourth channel structure, the second metal cap having a different work function from another portion of the second gate structure.

5 . The semiconductor device of claim 4 , wherein the first metal cap and the second metal cap have a substantially same work function.

6 . The semiconductor device of claim 5 , wherein the first channel structure includes a channel material, the first gate structure comprises a first metal layer that has a first work function closer to a valence band edge of the channel material, and the second gate structure comprises a second metal layer that has a second work function closer to a conduction band edge of the channel material.

7 . The semiconductor device of claim 1 , wherein the first metal cap has a mid-gap work function with regard to a bandgap of a channel material in the first channel structure.

8 . The semiconductor device of claim 7 , wherein the first metal cap includes at least one of: titanium nitride, tantalum silicon nitride, or tantalum nitride.

9 . The semiconductor device of claim 1 , wherein the first channel structure has an oval shape in a channel width cross-section.

10 . A method for forming a semiconductor device, comprising:
forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device, the first stack of channel structures including a first channel structure and a second channel structure; and forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure, the first metal cap having a different work function from another portion of the first gate structure.

11 . The method of claim 10 , wherein forming the first gate structure that wraps around the first stack of channel structures with the first metal cap between the first channel structure and the second channel structure further comprises:
depositing a layer of a specific metal around the first channel structure and the second channel structure to fill a gap between the first channel structure and the second channel structure; and etching the specific metal layer to form the first metal cap.

12 . The method of claim 11 , further comprising:
depositing a first metal layer that has a different work function from the specific metal to wrap the first stack of channel structures.

13 . The method of claim 11 , further comprising:
controlling parameters of depositing the specific metal layer to have a thickness; and controlling parameters of etching the specific metal layer to form the first metal cap that has a smaller dimension than the first channel structure in a channel width cross-section.

14 . The method of claim 10 , further comprising:
forming a second stack of channel structures that extends between a source terminal and a drain terminal of a second transistor in a second region of the semiconductor device; and forming a second gate structure that wraps around the second stack of channel structures with a second metal cap between a third channel structure and a fourth channel structure in the second stack of channel structures, the second metal cap having a different work function from another portion of the second gate structure.

15 . The method of claim 14 , wherein forming the first gate structure and the second gate structure further comprise:
depositing a layer of a specific metal that respectively wraps around the first stack of channel structures and the second stack of channel structures and fills a gap between the first channel structure and the second channel structure and a gap between the third channel structure and the fourth channel structure; and etching the specific metal layer to form the first and second metal caps that have a substantially same work function.

16 . The method of claim 15 , further comprising:
depositing a first metal layer that has a first band-edge work function, the first metal layer forming the first gate structure for the first transistor and a dummy second gate structure for the second transistor; selectively etching the dummy second gate structure without etching the first gate structure; and depositing a second metal layer that has a second band-edge work function that is different from the first band-edge function, the second metal layer forming the second gate structure for the second transistor.

17 . The method of claim 10 , wherein forming the first gate structure that wraps around the first stack of channel structures with the first metal cap between the first channel structure and the second channel structure further comprises:
depositing a specific metal having a mid-gap work function with regard to a bandgap of a channel material for the first channel structure; and etching the specific metal layer to form the first metal cap that have the mid-gap work function.

18 . The method of claim 17 , wherein depositing the specific metal layer comprises:
depositing at least one of titanium nitride, tantalum silicon nitride, or tantalum nitride.

19 . The method of claim 10 , wherein forming the first stack of channel structures comprises:
forming fins including first epitaxial layers of a first composition of materials interposed by second epitaxial layers of a second composition of materials; and selectively etching the first epitaxial layers to form the first stack of channel structures of the second epitaxial layers.

20 . A semiconductor device, comprising:
a transistor that is formed on a substrate of the semiconductor device, the transistor comprising:
multiple channel structures that are stacked in a vertical direction above the substrate, the multiple channel structures extending between a source terminal and a drain termina

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Ju Shi Ning
• Tsai Ching-Wei
• Cheng Kuan-Lun
• Wang Chih-Hao

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/66553

  Electricity · mapped topic

• H01L21/3086

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic