Gate metal patterning for tight pitch applications

Patent metadata

Field	Value
Publication number	US-10103065-B1
Application number	US-201715496610-A
Country	US
Kind code	B1
Filing date	Apr 25, 2017
Priority date	Apr 25, 2017
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

First claim

What is claimed is:

1. A method of fabricating dual work function metal gate transistors, comprising:
obtaining a first structure including:
a substrate having a first region and a second region,
a first FET structure on the first region of the substrate, the first FET structure including a semiconductor channel region and a dielectric layer adjoining the semiconductor channel region,
a second FET structure on the second region of the substrate, the second FET structure including a semiconductor channel region and a dielectric layer adjoining the semiconductor channel region,
a first gate metal layer extending over the first and second regions of the substrate and adjoining the dielectric layers of the first and second FET structures, and
a mask covering the first FET structure;

subjecting the first structure to an etching process, thereby:
removing a first portion of the first gate metal layer from between the mask and the substrate, thereby forming a recess between the mask and the substrate, and
partially removing a second portion of the first gate metal layer from the second FET structure while leaving a remaining portion of the first gate metal layer on the second FET structure;

sealing the recess;
removing the remaining portion of the first metal gate layer from the second FET structure subsequent to sealing the recess;
removing the mask subsequent to removing the remaining portion of the first metal gate layer from the second FET structure, and
forming a second gate metal layer on the first and second FET structures, the second gate metal layer adjoining the dielectric layer of the second FET structure and having a different work function value than the first gate metal layer.

2. The method of claim 1 , wherein the first and second FET structures are nanosheet field-effect transistor structures.

3. The method of claim 1 , wherein the substrate further includes a shallow trench isolation region separating the first and second regions.

4. The method of claim 3 , wherein sealing the recess includes reflowing the mask.

5. The method of claim 3 , wherein sealing the recess includes depositing a liner on the structure such that a portion of the liner extends within the recess and seals the first gate metal layer beneath the mask, the method further including partially removing the liner from the structure such that the portion of the liner that seals the first gate metal layer remains within the recess.

6. The method of claim 5 , wherein the liner is an oxide liner deposited using atomic layer deposition.

7. The method of claim 1 , wherein each of the first and second FET structures includes a stack of nanosheet channel layers, wherein partially removing the first portion of the first gate metal layer from the second FET structure includes introducing a wet etch solution to the second FET structure and removing the wet etch solution while the remaining portion of the first gate metal layer remains between each of the nanosheet channel layers.

8. The method of claim 7 , wherein removing the remaining portion of the first gate metal layer includes introducing a further wet etch solution to the second FET structure.

9. The method of claim 1 , wherein sealing the recess includes reflowing the mask.

10. The method of claim 9 , wherein the mask is an organic planarizing layer.

11. The method of claim 1 , wherein each of the first and second FET structures includes a stack of nanosheet channel layers, the stack of nanosheet channel layers of the first FET structure being spaced from the stack of nanosheet channel layers of the second FET structure by a distance between thirty nanometers and fifty nanometers.

12. The method of claim 11 , wherein the nanosheet channel layers have widths between ten and fifty nanometers.

Assignees

• IBM

Inventors

• Mochizuki Shogo
• Reznicek Alexander
• Rubin Joshua M
• Wang Junli

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0673

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic