Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12563738-B2
Application number	US-202218069398-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Feb 28, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate and extending in a second direction, and a plurality of channel layers on the active region. The plurality of channel layers are spaced apart from each other in a third direction perpendicular to an upper surface of the substrate. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers include at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions are on both sides of the gate electrode, and the source/drain regions are in contact with the plurality of channel layers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate including an active region extending in a first direction; a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region; a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, and the plurality of channel layers surrounded by the gate electrode; a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage; and source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the plurality of channel layers.

2 . The semiconductor device of claim 1 , wherein each of the plurality of dielectric layers has a different thickness.

3 . The semiconductor device of claim 1 , wherein each of the plurality of dielectric layers includes a ferroelectric material having a different coercive field.

4 . The semiconductor device of claim 1 , wherein at least one of the plurality of dielectric layers defines a structure including alternately stacked first and second ferroelectric layers, each of the first and second ferroelectric layers including a different material.

5 . The semiconductor device of claim 1 , wherein the plurality of dielectric layers include at least one of hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), scandium (Sc), or oxides thereof.

6 . The semiconductor device of claim 5 , wherein the plurality of dielectric layers include hafnium oxide doped with at least one of zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), or scandium (Sc).

7 . The semiconductor device of claim 1 , wherein
each of the plurality of dielectric layers includes a first layer sequentially stacked with a second layer, and the first layer does not include a ferroelectric material and the second layer includes a ferroelectric material.

8 . The semiconductor device of claim 1 , wherein each of the plurality of channel layers has a different width in the second direction.

9 . The semiconductor device of claim 1 , further comprising:
a channel separator penetrating through the plurality of channel layers in the third direction, the channel separator dividing the plurality of channel layers into first and second layers in the second direction.

10 . The semiconductor device of claim 9 , wherein
the plurality of dielectric layers includes a first dielectric layer surrounding the first layer, and a second dielectric layer surrounding the second layer, and first and second dielectric layers at a same height level each have a different coercive voltage.

11 . The semiconductor device of claim 1 , wherein the plurality of channel layers include at least one of polycrystalline silicon (Si), silicon germanium (SiGe), an oxide semiconductor material, or a semiconductor material including a two-dimensional transition metal chalcogenide compound.

12 . A semiconductor device comprising:
a substrate including an active region extending in a first direction; a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region; a first channel layer, a second channel layer, and a third channel layer spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, wherein the first channel layer, the second channel layer and the third channel layer are sequentially stacked on the active region, and wherein the first channel layer, the second channel layer and the third channel layer are surrounded by the gate electrode; a first dielectric layer surrounding the first channel layer, a second dielectric layer surrounding the second channel layer, and a third dielectric layer surrounding the third channel layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the third direction on the active region, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer include at least one of a ferroelectric material or an anti-ferroelectric material, and wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer has a different thickness; and source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the first channel layer, the second channel layer and the third channel layer.

13 . The semiconductor device of claim 12 , wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness greater than the first thickness, and the third dielectric layer has a third thickness greater than the second thickness.

14 . The semiconductor device of claim 12 , wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer has a thickness in a range of 1 nm to 30 nm.

15 . The semiconductor device of claim 12 , wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer has a different coercive voltage.

16 . A semiconductor device comprising:
a memory cell array including a plurality of memory elements; and a peripheral circuit region including peripheral circuits configured to control the memory cell array, wherein each of the plurality of memory elements includes an active region extending in a first direction, a gate electrode intersecting the active region, the gate electrode extending in a second direction, a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the active region, and the plurality of channel layers surrounded by the gate electrode, and a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and wherein in each of the plurality of memory elements, a number of the plurality of channel layers is N, where N is a natural number equal to or greater than 2, and each of the plurality of memory elements is configured to store N bits of data or less.

17 . The semiconductor device of claim 16 , wherein the peripheral circuit region is configured to sequentially apply a first program voltage and a second program voltage to the gate electrode of a selected memory element in a program operation of writing first data to a selected one of the plurality of memory elements, wherein the first program voltage has a different sign than the second program voltage.

18 . The semiconductor device of claim 17 , wherein the first program voltage has a different magnitude than the second program voltage.

19 . The semiconductor device of claim 17 , wherein a magnitude of the first program voltage is greate

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ha Daewon
• Lee Kyunghwan

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10B51/40

  characterised by the peripheral circuit region · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title