Method for forming a nanowire device

Patent metadata

Field	Value
Publication number	US-10847424-B2
Application number	US-201916449118-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Jun 22, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.

First claim

What is claimed is:

1. A method of forming a nanowire device, the method comprising:
providing a substrate containing nanowires between vertical spacers;
selectively depositing a high-k film on the nanowires relative to the vertical spacers; and
selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers.

2. The method of claim 1 , further comprising:
selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, wherein the dielectric material has a lower dielectric constant than the high-k film.

3. The method of claim 2 , wherein selectively depositing the dielectric material on the vertical spacers includes depositing sufficient dielectric material to reduce gate-to-drain capacitance in the nanowire device.

4. The method of claim 1 , further comprising:
depositing a dielectric material on the vertical spacers above the nanowires after selectively depositing the metal-containing gate electrode layer, wherein the dielectric material has a lower dielectric constant than the high-k film.

5. The method of claim 1 , further comprising:
prior to selectively depositing the high-k film, exposing the substrate to an isotropic oxidizing plasma that forms an oxide layer on the nanowires.

6. The method of claim 5 , further comprising:
removing the oxide layer from the nanowires.

7. The method of claim 1 , wherein the nanowires consist of Si, SiGe, or both Si and SiGe.

8. The method of claim 1 , wherein the vertical spacers contain a SiCOH material, a dielectric material with a dielectric constant less than about 7 , or airgap spacers.

9. The method of claim 1 , wherein the high-k film includes HfO 2 , ZrO 2 , TiO 2 , or Al 2 O 3 .

10. The method of claim 1 , wherein the nanowires consist of Si and the metal-containing gate electrode layer contains TiSiN, TiA 1 C, Ti-rich TiN, W, WN x , Mo, or Pt.

11. The method of claim 1 , wherein the nanowires consist of SiGe and the metal-containing gate electrode layer contains TiN, TiON, Ru, W, WN x , Mo, or Pt.

12. The method of claim 1 , further comprising depositing a dielectric threshold voltage adjustment layer on the high-k film.

13. The method of claim 12 , wherein the nanowires consist of Si and the dielectric threshold voltage adjustment layer includes La 2 O 3 or Y 2 O 3 .

14. The method of claim 12 , wherein the nanowires consist of SiGe and the dielectric threshold voltage adjustment layer includes Al 2 O 3 .

15. The method of claim 1 , further comprising exposing the high-k film to an isotropic oxidizing plasma that forms an oxide layer at an interface of the nanowires and the high-k film.

16. The method of claim 1 , wherein the selective depositing the high-k film includes blocking the high-k film deposition on the vertical spacers.

17. The method of claim 16 , wherein the blocking includes forming self-assembled monolayers (SAMs) on the vertical spacers.

18. The method of claim 1 , wherein the selective depositing the metal-containing gate electrode layer includes blocking the metal-containing gate electrode layer deposition on the vertical spacers.

19. The method of claim 18 , wherein the blocking includes forming self-assembled monolayers (SAMs) on the vertical spacers.

20. A method of forming a nanowire device, the method comprising:
providing a substrate containing Si, SiGe, or both Si and SiGe nanowires between vertical spacers;
selectively depositing a dielectric material on the vertical spacers, wherein the selectively depositing the dielectric material on the vertical spacers includes depositing sufficient dielectric material to reduce gate-to-drain capacitance in the nanowire device;
selectively depositing a high-k film on the nanowires relative to the vertical spacers by blocking the high-k film deposition on the vertical spacers, wherein the dielectric material has a lower dielectric constant than the high-k film; and
selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers by blocking the metal-containing gate electrode layer deposition on the vertical spacers.

Assignees

• Tokyo Electron Ltd

Inventors

• Tapily Kandabara
• Smith Jeffrey
• Leusink Gerrit

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title