Three-dimensional memory devices and fabricating methods thereof

Patent metadata

Field	Value
Publication number	US-12557299-B2
Application number	US-202218089495-A
Country	US
Kind code	B2
Filing date	Dec 27, 2022
Priority date	Dec 22, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of first type memory cells; a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells; a third semiconductor structure comprising a first peripheral circuit; and a fourth semiconductor structure comprising a second peripheral circuit; wherein the first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.

2 . The 3D memory device of claim 1 , wherein:
the first semiconductor structure further comprises a first semiconductor layer; and the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer.

3 . The 3D memory device of claim 2 , wherein:
the second semiconductor structure further comprises a second semiconductor layer; and the array of second type memory cells comprises an array of multi-gate dynamic flash memory (DFM) cells formed on the second semiconductor layer.

4 . The 3D memory device of claim 3 , wherein:
the third semiconductor structure further comprises a third semiconductor layer; and the first peripheral circuit comprises a plurality of first type transistors having a first operating voltage on the third semiconductor layer.

5 . The 3D memory device of claim 4 , wherein:
the fourth semiconductor structure further comprises a fourth semiconductor layer; and the second peripheral circuit comprises a plurality of third type transistors having a third operating voltage on the fourth semiconductor layer, wherein the third operating voltage is lower than the first operating voltage.

6 . The 3D memory device of claim 5 , wherein:
the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage; and the third and fourth semiconductor layers have different thicknesses.

7 . The 3D memory device of claim 6 , further comprising:
a first bonding interface between the first semiconductor structure and the third semiconductor structure; a second bonding interface between the second semiconductor structure and the fourth semiconductor structure; and a third bonding interface between the first semiconductor structure and the second semiconductor structure.

8 . The 3D memory device of claim 7 , wherein:
the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the HV circuit; and the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the LLV circuit.

9 . The 3D memory device of claim 8 , wherein:
the first semiconductor structure further comprises a first through contact penetrating the first semiconductor layer to couple the first interconnect; the second semiconductor structure further comprises a second through contact penetrating the second semiconductor layer to couple the second interconnect; the third semiconductor structure further comprises a third through contact penetrating the third semiconductor layer to couple the third interconnect; and the fourth semiconductor structure further comprises a fourth through contact penetrating the fourth semiconductor layer to couple the fourth interconnect.

10 . The 3D memory device of claim 9 , wherein:
the third semiconductor structure or the fourth semiconductor structure further comprises a pad-out interconnect layer including a contact pad in electrical connection with the third through contact or the fourth through contact.

11 . A system, comprising:
a memory device configured to store data, and comprising:
a first semiconductor structure comprising an array of first type memory cells,
a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells,
a third semiconductor structure comprising a first peripheral circuit, and
a fourth semiconductor structure comprising a second peripheral circuit,
wherein the first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction; and
a memory controller coupled to the memory device and configured to control the array of first type memory cells and the array of second type memory cells through the first peripheral circuit and the second peripheral circuit.

12 . A method of forming a three-dimensional (3D) memory device, comprising:
forming a first semiconductor structure comprising an array of first type memory cells; forming a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells; forming a third semiconductor structure comprising a first peripheral circuit; forming a fourth semiconductor structure comprising a second peripheral circuit; bonding the first semiconductor structure to the third semiconductor structure; bonding the second semiconductor structure to the fourth semiconductor structure; and bonding the first semiconductor structure to the second semiconductor structure.

13 . The method of claim 12 , wherein forming the first semiconductor structure comprises:
forming an array of NAND memory strings on a first semiconductor layer; forming a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; and forming a first through contact in the first semiconductor layer to couple the first interconnect.

14 . The method of claim 13 , wherein forming the second semiconductor structure comprises:
forming an array of multi-gate dynamic flash memory (DFM) cells on a second semiconductor layer; forming a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; and forming a second through contact in the second semiconductor layer to couple the second interconnect.

15 . The method of claim 14 , wherein forming the third semiconductor structure comprises:
forming a first circuit including a plurality of first type transistors having a first operating voltage on a third semiconductor layer; and forming a third interconnect layer comprising a third interconnect coupled to the first circuit.

16 . The method of claim 15 , wherein forming the fourth semiconductor structure comprises:
forming a third circuit including a plurality of third transistors having a third operating voltage on a fourth semiconductor layer, wherein the third operating voltage is lower than the first operating voltage; and forming a fourth interconnect layer comprising a fourth interconnect coupled to the third circuit.

17 . The method of claim 12 , wherein forming the third semiconductor structure or forming the fourth semiconductor structure further comprises:
forming a second circuit including a plurality of second type transistors having a second operating voltage; wherein the seco

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Yang Yuancheng
• Zhou Wenxi
• Xia Zhiliang
• Zhao Dongxue
• Yang Tao
• Liu Lei
• Wang Di
• Huo Zongliang

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title