Multi-die structure and method for forming same

Patent metadata

Field	Value
Publication number	US-10553569-B2
Application number	US-201715699373-A
Country	US
Kind code	B2
Filing date	Sep 8, 2017
Priority date	Apr 13, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A device includes a semiconductor structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side contact metal, a molding compound layer and a backside contact metal, and wherein the front side contact metal is between the plurality of bottom package bumps and the molding compound layer and a metal shielding layer on a top surface, sidewalls of the semiconductor structure and portions of a bottom surface of the bottom package, wherein the metal shielding layer is in direct contact with an edge of at least one of the front side contact metal and the backside contact metal.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor structure comprising a top package over a bottom package, wherein the bottom package comprises a first interconnect structure, a second interconnect structure, a molding compound layer between the first interconnect structure and the second interconnect structure, and a semiconductor die in the molding compound layer, and wherein a contact metal of the semiconductor structure is formed in a dielectric layer of the first interconnect structure or the second interconnect structure, wherein the contact metal has an edge substantially level with a surface of the dielectric layer, wherein each of the first interconnect structure and the second interconnect structure comprises a plurality of redistribution lines; and
a metal shielding layer on a top surface of the top package, sidewalls of the top package, sidewalls of the bottom package, and a bottom surface of the bottom package, wherein the metal shielding layer is in direct contact with the edge of the contact metal, wherein the metal shielding layer is a single continuous layer, wherein a thickness of the metal shielding layer along the sidewalls of the top package is greater than a thickness of the metal shielding layer along the bottom surface of the bottom package, wherein the metal shielding layer is a distinct layer from the first interconnect structure and the second interconnect structure.

2. The apparatus of claim 1 , wherein:
a substrate portion of the semiconductor die is in contact with the first interconnect structure;
an interconnect portion of the semiconductor die is in contact with the second interconnect structure; and
bumps of the top package are in contact with the first interconnect structure.

3. The apparatus of claim 2 , wherein:
the contact metal is a first redistribution line of the first interconnect structure.

4. The apparatus of claim 2 , wherein:
the contact metal is a first redistribution line of the second interconnect structure.

5. The apparatus of claim 2 , wherein:
the metal shielding layer is in contact with sidewalls and a top surface of a redistribution line of the first interconnect structure.

6. The apparatus of claim 2 , wherein:
the contact metal is a via connected to a redistribution line of the second interconnect structure.

7. The apparatus of claim 1 further comprising a plurality of through vias extending through the molding compound layer to electrically couple the first interconnect structure to the second interconnect structure.

8. The apparatus of claim 1 further comprising a plurality of package bumps on the bottom surface of the bottom package.

9. A device comprising:
a semiconductor structure comprising a package-on-package structure, the package-on-package structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side contact metal, a molding compound layer and a backside contact metal, and wherein the front side contact metal is between the plurality of bottom package bumps and the molding compound layer, wherein the front side contact metal is a front side redistribution line, and wherein the backside contact metal is a backside redistribution line; and
a metal shielding layer being a single continuous layer extending from a top surface of the top package along sidewalls of the semiconductor structure to a bottom surface of the bottom package, wherein the metal shielding layer is in direct contact with an edge of at least one of the front side contact metal and the backside contact metal, wherein a thickness of the metal shielding layer over sidewalls of the package-on-package structure is greater than a thickness of the metal shielding layer over the bottom surface of the bottom package.

10. The device of claim 9 , further comprising:
a semiconductor die embedded in the molding compound layer, wherein an interconnect portion of the semiconductor die is in direct contact with the front side redistribution line.

11. The device of claim 9 , wherein:
the metal shielding layer is in direct contact with an edge of the backside redistribution line.

12. The device of claim 9 , wherein:
the metal shielding layer is in direct contact with an edge of the front side redistribution line.

13. The device of claim 9 , wherein:
the metal shielding layer is connected to the front side redistribution line through a via formed on the front side redistribution line.

14. The device of claim 9 , wherein:
the metal shielding layer over the bottom surface of the bottom package occupies edge portions of the bottom surface of the bottom package.

15. The device of claim 9 , wherein the metal shielding layer contacts an upper surface of the bottom package.

16. The device of claim 9 , wherein the metal shielding layer contacts a bottom surface of the bottom package.

17. A device comprising: a package-on-package structure comprising a top package on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side redistribution line, a molding compound layer and a backside redistribution line, and wherein the front side redistribution line is between the plurality of bottom package bumps and the molding compound layer, the package-on-package structure comprising a semiconductor die embedded in the molding compound layer, wherein an interconnect portion of the semiconductor die is in direct contact with the front side redistribution line, the package-on-package structure comprising a first via and a second via, the first via extending through the molding compound layer and coupled between the front side redistribution line and the backside redistribution line, the second via extending through the molding compound layer and coupled between the front side redistribution line and the backside redistribution line, wherein the semiconductor die is between the first via and the second via; and a metal shielding layer in direct contact with a top surface of the top package, sidewalls of the top package and portions of the bottom package, wherein the metal shielding layer is a single continuous layer in direct contact with an edge of at least one of the front side redistribution line and the backside redistribution line; wherein a thickness of the metal shielding layer over sidewalls of the package-on-package structure is greater than a thickness of the metal shielding layer over the bottom surface of the bottom package.

18. The device of claim 17 , wherein the metal shielding layer contacts an upper surface of the bottom package.

19. The device of claim 17 , wherein the metal shielding layer completely is in direct contact with both the front side redistribution line and the backside redistribution line.

20. The device of claim 17 , wherein the metal shielding layer is in direct contact with a bottom surface of the bottom package.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Tsai Po-Hao
• Lin Jing-Cheng
• Cheng Li-Hui

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/741

  the auxiliary support including a cavity for storing a finished or partly finished device during manufacturing or mounting, e.g. for an IC package or for a chip · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title