Semiconductor structure and method manufacturing the same

Patent metadata

Field	Value
Publication number	US-12347785-B2
Application number	US-202016852567-A
Country	US
Kind code	B2
Filing date	Apr 20, 2020
Priority date	Sep 29, 2019
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

First claim

What is claimed is:

1. A semiconductor device, comprising:
system-on-integrated chips, each comprising a die stack having a base tier and stacking tiers stacked on the base tier, wherein the base tier comprises a base semiconductor die comprising a first semiconductor substrate and first through vias penetrating the first semiconductor substrate, and each of the stacking tiers comprises at least one stacking semiconductor die comprising a second semiconductor substrate and second through vias penetrating the second semiconductor substrate, a plurality of contact pads contacting the second through vias, and a passivation layer laterally covering the plurality of contact pads, wherein top surfaces of the plurality of contact pads is substantially coplanar with and substantially leveled with a top surface of the passivation layer, and the plurality of contact pads and the passivation layer are interposing between two adjacent stacking tiers of the stacking tiers, wherein a projection of the at least one stacking semiconductor die of each of the stacking tiers is entirely disposed within a projection of the base semiconductor die in a stacking direction of the base tier and the stacking tiers;
a first redistribution circuit structure, located on and electrically connected to the system-on-integrated chips, wherein the stacking tiers of each of the system-on-integrated chips are disposed between the base tier of a respective one of the system-on-integrated chips and the first redistribution circuit structure, wherein a sidewall of the first semiconductor substrate is aligned with a sidewall of the first redistribution circuit structure;
a second redistribution circuit structure, disposed between and electrically coupled to two adjacent stacking tiers of the stacking tiers of each of the system-on-integrated chips, the second redistribution circuit structure being in physical contact with the plurality of contact pads comprised in an underlying stacking tier of the two adjacent stacking tiers;
first conductive elements, directly connected on the first redistribution circuit structure, wherein the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive elements; and
conductive features, disposed over and electrically coupled to the system-on-integrated chips, wherein the system-on-integrated chips are located between the first conductive elements and the conductive features, and the conductive features are spacing away from an insulating encapsulation covering the base semiconductor die and the at least one stacking semiconductor die of each of the stacking tiers of the system-on-integrated chips,
wherein surfaces of the first conductive elements not covered by the first redistribution circuit structure and a surface of the first redistribution circuit structure exposed by the first conductive elements together constitute an outermost surface of the semiconductor device, and the conductive features are disposed over a side of the system-on-integrated chips opposing to the outermost surface.

2. The semiconductor device of claim 1 ,
wherein a material of the insulating encapsulation comprises a dielectric material or a molding compound,
wherein the first semiconductor substrate comprises a silicon substrate, and the first redistribution circuit structure comprises one or more than one inter-layer dielectric layer and one or more than one patterned conductive layer alternatively arranged,
wherein a sidewall of the semiconductor device comprises the sidewall of the first semiconductor substrate, the sidewall of the first redistribution circuit structure, and a sidewall of the insulating encapsulation, and
wherein the first conductive elements each comprise an under-ball metallurgy pattern and a conductive terminal, and the under-ball metallurgy pattern is interposed between the first redistribution circuit structure and the conductive terminal.

3. The semiconductor device of claim 1 ,
wherein a hybrid bonding interface is between the base semiconductor die of the base tier and the at least one stacking semiconductor die of a respective one of the stacking tiers.

4. The semiconductor device of claim 1 , wherein the plurality of contact pads laterally covered by the passivation layer have sidewalls completely covered by the passivation layer, and the second redistribution circuit structure comprises a plurality of dielectric layers and a plurality of conductive layers alternatively arranged.

5. The semiconductor device of claim 1 , further comprising:
a substrate having a circuitry therein, wherein the system-on-integrated chips are mounted on and electrically connected to the substrate through the first conductive elements; and
second conductive elements, disposed on the substrate and electrically connected to the circuitry, wherein the substrate is located between the first conductive elements and the second conductive elements.

6. The semiconductor device of claim 5 , further comprising:
a thermal dissipating film, located on back surfaces of the system-on-integrated chips and thermally coupled to the system-on-integrated chips, wherein the system-on-integrated chips are located between the first redistribution circuit structure and the thermal dissipating film; and
a heat dissipating module, located on thermal dissipating film and thermally coupled to the system-on-integrated chips through the thermal dissipating film, wherein the heat dissipating module comprises:
a conductive plate, extending along the back surfaces of the system-on-integrated chips;
a plurality of pillars, disposed on a first surface of the conductive plate and extending away from the first surface of the conductive plate; and
a plurality of pins, disposed on a second surface of the conductive plate and extending away from the second surface of the conductive plant, wherein the pins penetrate through the thermal dissipating film and are in contact with the back surfaces of the system-on-integrated chips, wherein the conductive plate is located between the plurality of pillars and the plurality of pins.

7. The semiconductor device of claim 6 , wherein the heat dissipating module further comprises:
a flange portion, located on the second surface of the conductive plate and at a periphery of the second surface; and
a mechanical fastener, penetrating through the flange portion and inserted into the substrate.

8. A semiconductor device, comprising:
system-on-integrated chips, each comprising a die stack comprising:
a base tier, comprising at least one first semiconductor die comprising a first semiconductor substrate and first through vias penetrating the first semiconductor substrate;
inner tiers, located over the base tier and sequentially stacked on one another, each of the inner tiers comprising second semiconductor dies, a plurality of contact pads, a passivation layer and conductive pillars, the second semiconductor dies each comprising a second semiconductor substrate and second through vias penetrating the second semiconductor substrate, the plurality of contact pads disposed on and contacting the second through vias of at least one inner tier of the inner tiers, and the passivation layer laterally covering the plurality of contact pads and extending onto the at least one inner tier of the inner tiers, wherein top surfaces of the plurality of contact pads are substantially coplanar with and substantially leveled with a top surface of the passivation layer, wherein a projection of at least one of the second semiconductor dies is entirely disposed within a projection of the at least one first semiconductor die in a stacking direction of the base tier and the inner tiers;
a redistribution structure, disposed between and e

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yee Kuo-Chung

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/0198

  batch processes · CPC title