Semiconductor device with variable gate-to-channel spacing

Patent metadata

Field	Value
Publication number	US-12557291-B2
Application number	US-202418591076-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Jun 25, 2020
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first structure including circuit elements; and a second structure on the first structure and overlapping the first structure in a vertical direction, wherein the second structure includes:
a stack structure including gate layers and interlayer insulating layers alternately stacked in the vertical direction;
a first pattern layer below the stack structure and disposed between the first structure and the stack structure and spaced apart from the gate layers;
a vertical memory structure penetrating through the stack structure in the vertical direction;
a bit line on the stack structure and the vertical memory structure; and
a contact plug between the bit line and the vertical memory structure,
wherein the vertical memory structure includes:
a core region;
a channel layer on a side surface of the core region; and
a data storage structure on an outer side surface of the channel layer,
wherein the first pattern layer includes:
a first pattern portion overlapping the gate layers in the vertical direction; and
a second pattern portion extending from the first pattern portion in a direction away from the first structure and contacting the channel layer,
wherein the gate layers include a first gate layer closest to the first structure and a second gate layer furthest from the first structure, wherein a distance between the first structure and an upper end of the second pattern portion is greater than a distance between the first structure and the first gate layer, wherein the first pattern portion is at a lower level than a lower surface of the first gate layer, with respect to the first structure, and wherein the upper end of the second pattern portion is at a higher level than the lower surface of the first gate layer, with respect to the first structure.

2 . The semiconductor device of claim 1 , wherein the first pattern layer includes polysilicon.

3 . The semiconductor device of claim 1 , wherein a distance between the first structure and the core region is less than a distance between the first structure and the first pattern layer.

4 . The semiconductor device of claim 1 , wherein the second pattern portion contacts the core region.

5 . The semiconductor device of claim 1 , wherein the data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer, and
wherein the second dielectric layer is between the data storage layer and the channel layer.

6 . The semiconductor device of claim 5 , wherein the data storage layer has a first storage end portion contacting the second pattern portion, and
wherein a distance between the first structure and the first storage end portion is greater than the distance between the first structure and the first gate layer.

7 . The semiconductor device of claim 5 , wherein the first dielectric layer has a first dielectric end portion contacting the second pattern portion,
wherein the second dielectric layer has a second dielectric end portion contacting the second pattern portion, and wherein a distance between the first structure and the first dielectric end portion is different from a distance between the first structure and the second dielectric end portion.

8 . The semiconductor device of claim 5 , wherein the first dielectric layer has a first dielectric end portion contacting the second pattern portion,
wherein the second dielectric layer has a second dielectric end portion contacting the second pattern portion, and wherein a distance between the first structure and the first dielectric end portion is less than a distance between the first structure and the second dielectric end portion.

9 . The semiconductor device of claim 5 , wherein the first dielectric layer has a first dielectric end portion contacting the second pattern portion,
wherein the second dielectric layer has a second dielectric end portion contacting the second pattern portion, and wherein a distance between the first structure and the first dielectric end portion is less than the distance between the first structure and the first gate layer.

10 . The semiconductor device of claim 1 , wherein the second structure further includes a second pattern layer between the first pattern portion and the stack structure, and
wherein the second pattern layer includes polysilicon.

11 . The semiconductor device of claim 1 , wherein the second structure further includes a third pattern layer between the first pattern layer and the first structure and between the core region and the first structure, and
wherein a thickness of the third pattern layer is greater than a thickness of the first pattern portion.

12 . The semiconductor device of claim 1 , wherein the channel layer has a first channel end portion contacting the second pattern portion, and
wherein a distance between the first structure and the first channel end portion is greater than a distance between the first structure and the first gate layer.

13 . The semiconductor device of claim 12 , wherein the channel layer has a second channel end portion opposite to the first channel end portion,
wherein the second gate layer has a first surface facing the first gate layer and a second surface opposite to the first surface, and wherein a distance between the first structure and the second channel end portion is less than a distance between the first structure and the second surface of the second gate layer.

14 . The semiconductor device of claim 13 , wherein the distance between the first structure and the second channel end portion is greater than a distance between the first structure and the first surface of the second gate layer.

15 . The semiconductor device of claim 13 , wherein the vertical memory structure further includes a pad pattern on the core region, and
wherein the pad pattern contacts the second channel end portion of the channel layer.

16 . The semiconductor device of claim 1 , wherein the second structure further includes a separation structure penetrating through the stack structure, and
wherein a width of the separation structure is greater than a width of the vertical memory structure.

17 . The semiconductor device of claim 1 , wherein the first pattern portion extends in a horizontal direction and overlaps the stack structure in a vertical direction, and
wherein a width of the first pattern portion in the horizontal direction is greater than a width of the second pattern portion in the horizontal direction.

18 . A semiconductor device comprising:
a first structure including circuit elements; and a second structure on the first structure, wherein the second structure includes:
a stack structure including gate layers and interlayer insulating layers alternately stacked in a vertical direction;
a pattern structure below the stack structure and disposed between the first structure and the stack structure and spaced apart from the gate layers;
a vertical memory structure penetrating through the stack structure in the vertical direction;
a bit line on the stack structure and the vertical memory structure; and
a contact plug between the bit line and the vertical memory structure,
wherein the vertical memory structure includes:
a core region;
a channel layer on a side surface of the core region;
a data storage structure on an outer side surface of the channel layer; and
a pad pattern on an upper surface of the core region,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Wukang
• Park Sejun
• Bang Hyoje
• Lee Jaeduk
• Lee Junghoon

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title