Multi-deck memory device with access line and data line segregation between decks and method of operation thereof

Patent metadata

Field	Value
Publication number	US-10074430-B2
Application number	US-201615231011-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Aug 8, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;
access lines coupled to the first and second memory cell strings, wherein the first and second memory cell blocks share the access lines; and
transistors, each of the transistors coupled to a respective access line of the access lines, wherein the transistors include a common gate.

2. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus; and
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks, wherein the buffer circuitry includes:
a first buffer circuit;
a first transistor coupled between the first buffer circuit and one of the first conductive paths;
a second buffer circuit; and
a second transistor coupled between the second buffer circuit and one of the second conductive paths.

3. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus; and
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks, wherein the buffer circuitry includes:
a buffer circuit;
a first transistor coupled between the buffer circuit and one of the first conductive paths; and
a second transistor coupled between the buffer circuit and one of the second conductive paths.

4. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;
a first source select line coupled to each of the first memory cell strings, the first source select line to control first select transistors, each of the first select transistors being located along a segment of a respective pillar among pillars of the first memory cell strings;
a second source select line coupled to each of the second memory cell strings, the second source select line to control second select transistors, each of the second select transistors being located along a segment of a respective pillar among pillars of the second memory cell strings;
a first additional conductive path coupled to the first source select line and a driver circuit; and
a second additional conductive path coupled to the second source select line and the driver circuit, wherein the first additional conductive path is separate from the second additional conductive path.

5. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;
a first conductive line contacting a pillar of each of the first memory cell strings;
a second conductive line contacting a pillar of each of the second of memory cell strings;
a first additional conductive path coupled to the first conductive line and a driver circuit; and
a second additional conductive path coupled to the second conductive line and the driver circuit, wherein the first additional conductive path is separate from the second additional conductive path.

6. An apparatus comprising:
a substrate;
a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;
a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;
first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;
second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;
a first deck of memory cell strings located over the substrate, the first deck of memory cell strings being physically located in a first portion of a memory device of the apparatus, the first deck of memory cell strings including a first plurality memory cell blocks physically located in the first portion of the memory device, wherein the first memory cell block is included in the first plurality memory cell blocks; and
a second deck of memory cell strings located over the first deck of memory cell strings, the second deck of memory cell strings being physically located betw

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title