Three-dimensional memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10475807-B2
Application number	US-201415503833-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Aug 15, 2014
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings. In accordance with the three-dimensional memory manufacturing method of the present invention, the deep trenches of word-line in the TCAT three-dimensional device are replaced with deep-hole etching to realize the same function, thereby improving the integration density, simplifying the etching process of stacked structure, and maintaining the control performance of the metal gate.

First claim

The invention claimed is:

1. A method for manufacturing three-dimensional memory, comprising the steps of:
forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate;
etching the stack structure to expose the substrate, forming a plurality of first vertical openings in an array region located in a central region, the plurality of first vertical openings being disposed in a matrix in plan view;
forming a filling layer in each of the first openings;
etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings arranged so that each of at least a majority of the plurality of first openings is surrounded by a symmetrical arrangement of the second vertical openings;
forming a vertical channel layer and a drain in each of the second openings;
removing the filling layer by selective etching, re-exposing the first openings;
partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses;
forming a plurality of gate stack structures in the plurality of recesses;
forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings.

2. The method for manufacturing three-dimensional memory of claim 1 , wherein the first material layers, the second material layers and the filling layer have etching selectivity different from each other.

3. The method for manufacturing three-dimensional memory of claim 2 , wherein the materials of the first material layers, the second material layers and the filling layer are selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, amorphous germanium, DLC, amorphous carbon and the combinations thereof.

4. The method for manufacturing three-dimensional memory of claim 1 , wherein the size of the first openings is greater than or equal to that of the second openings.

5. The method for manufacturing three-dimensional memory of claim 1 , wherein the channel layer is a hollow structure comprising an insulator in the center.

6. The method for manufacturing three-dimensional memory of claim 1 , wherein after forming the common sources, further comprising forming an insulating layer on sidewalls of each of the first openings, forming a contact layer contacting the common source regions on sidewalls of the insulating layer and at the bottom of each of the first openings.

7. The method for manufacturing three-dimensional memory of claim 6 , wherein during or after forming the contact layers, further comprising controlling the deposition process parameters or etching back to ensure that the top surface of the contact layer is lower than the bottom of the topmost layer of the gate stack structure, and then backfilling with the insulating layer.

8. The method for manufacturing three-dimensional memory of claim 6 , wherein after forming the contact layer, further comprising partially removing the first material layers and the gate stack structure by etching to form a plurality of third openings, and depositing insulating material in each of the plurality of the third openings to form an isolation insulating region up to the topmost layer of the gate stack structures.

9. The method for manufacturing three-dimensional memory of claim 8 , wherein after forming the isolation insulating region, further comprising forming an interlayer dielectric layer on the device, etching the interlayer dielectric layer to form a plurality of fourth openings until the contact layer is exposed, and then filling with metal to form a common source wiring.

10. The method for manufacturing three-dimensional memory of claim 9 , wherein after forming a contact plug of the common source line, further comprising forming a second interlayer dielectric layer on the device, etching the second interlayer dielectric layer to form a plurality of fifth openings until the channel region is exposed, and then filling with metal to form a bit-line contact.

11. The method for manufacturing three-dimensional memory of claim 1 , wherein before forming the first openings by etching, further comprising etching the stack structure in the word-line contact region surrounding the array area to form stairs, sequentially exposing the ends of each of the first material layers and the second material layers.

12. A method for manufacturing three-dimensional memory, comprising the steps of:
forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate;
etching the stack structure to expose the substrate, meanwhile forming a plurality of vertical first openings as well as a plurality of second openings around each of the first openings in an array region located in a central region, the plurality of first vertical openings being disposed in a matrix in plan view and arranged so that each of at least a majority of the plurality of the first openings is surrounded by a symmetrical arrangement of the second vertical openings;
forming a filling layer in each of the first openings;
forming a vertical channel layer and a drain in each of the second openings;
removing the filling layers by selective etching, re-exposing the first openings;
partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses;
forming a gate stack structure in each of the recesses;
forming a common source on and/or in the substrate at the bottom of each of the first openings.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Huo Zongliang
• Liu Ming
• Jin Lei

Classifications

• H01L27/11578

  Electricity · mapped topic

• H01L28/00

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10D1/00 Primary

  Resistors, capacitors or inductors · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title