Three-dimensional memory and fabrication method for the same

Patent metadata

Field	Value
Publication number	US-12557279-B2
Application number	US-202217845308-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	Jun 21, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory, comprising:
forming a storage stack structure; forming a storage channel structure that penetrates through the storage stack structure, wherein a top of the storage channel structure comprises a first width in a first direction; forming a selection stack structure on the storage stack structure; forming a selection channel hole that penetrates through the selection stack structure to expose a portion of the storage channel structure, wherein a bottom of the selection channel hole comprises a second width and a top opening of the selection channel hole comprises a third width in the first direction; forming a second recessed opening at a top portion of the selection channel hole, wherein after reaming, a top opening of the second recessed opening comprises a fourth width in the first direction and the fourth width of the second recessed opening is larger than the third width of the selection channel hole, and wherein the forming the second recessed opening comprises:
removing a stop layer from the selection channel hole to expose a conductive layer;
removing a portion of the conductive layer, after removing the stop layer;
removing a portion of an insulating layer on a sidewall of the selection channel hole while forming the second recessing opening; and
enlarging the top opening of the selection channel hole to form the second recessed opening; and
forming a top selection gate (TSG) cut structure that penetrates through the selection stack structure along a second direction, wherein the TSG cut structure extends in a third direction, the second direction being perpendicular to the first direction and the third direction is perpendicular to the first direction.

2 . The method of claim 1 , wherein forming the selection channel hole further comprises forming the second width of the selection channel hole smaller than the first width of the top of the storage channel structure in the first direction.

3 . The method of claim 1 , further comprising, prior to forming the second recessed opening, forming a selection channel structure in the selection channel hole, wherein the selection channel structure penetrates through the selection stack structure and physically and electrically connects to the storage channel structure.

4 . The method of claim 3 , wherein the forming the selection channel structure comprises:
forming the insulating layer on an inner side wall surface and the bottom of the selection channel hole; selectively removing the insulating layer located at the bottom of the selection channel hole to expose the storage channel structure through isotropic etching; forming the conductive layer on a surface of the insulating layer covering a sidewall surface and the bottom of the selection channel hole; filling in the selection channel hole with a dielectric material to form a dielectric core; and forming the stop layer inside the selection channel hole.

5 . The method of claim 4 , wherein the forming the stop layer inside the selection channel hole comprises:
removing a portion of the dielectric core to form a first recessed opening at the top portion of the selection channel hole; and disposing the stop layer in the first recessed opening, wherein the disposing the stop layer comprises disposing silicon nitride.

6 . The method of claim 1 , further comprising forming a selection channel plug in the second recessed opening to contact the conductive layer of a selection channel structure after forming the second recessed opening, wherein the forming the selection channel plug comprises filling in the second recessed opening with a conductive material.

7 . The method of claim 1 , wherein the forming the TSG cut structure comprises:
forming a TSG cut that penetrates through the selection stack structure; and filling in the TSG cut with a dielectric material to form the TSG cut structure.

8 . The method of claim 1 , wherein the forming the 3D memory comprises:
forming a plurality of selection channel structures in rows in the second direction; forming the TSG cut structure between adjacent selection channel structure rows; and forming the TSG cut structure in a wave shape.

9 . The method of claim 3 , further comprising aligning the selection channel structure off-axis with the storage channel structure in the first direction to increase a distance between the selection channel structure and an adjacent TSG cut structure.

10 . The method of claim 1 , wherein the forming the storage stack structure further comprises forming a plurality of sub-storage stack structures and a plurality of sub-storage channel structures separated by TSG cut structures.

11 . The method of claim 6 , wherein the conductive layer of the selection channel structure and the selection channel plug comprise polysilicon.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Gao Tingting
• Xia Zhiliang
• Liu Xiaoxin
• Sun Changzhi
• Du Xiaolong

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title