Three-dimensional memory device including a string selection line gate electrode having a silicide layer

Patent metadata

Field	Value
Publication number	US-11792994-B2
Application number	US-202217659990-A
Country	US
Kind code	B2
Filing date	Apr 20, 2022
Priority date	Sep 24, 2019
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
a source structure;
a cell stack on the source structure, the cell stack including a plurality of mold layers and a plurality of word lines alternately stacked in a vertical direction;
an upper gate electrode on the cell stack;
a string selection line separation pattern on a sidewall of the upper gate electrode;
a vertical channel structure including a lower portion and an upper portion on the lower portion;
a bit line on the vertical channel structure; and
a plug between the bit line and the vertical channel structure,
wherein the lower portion penetrates through the cell stack,
wherein the upper portion penetrates through the upper gate electrode,
wherein the vertical channel structure includes:
a lower gap-fill pattern;
an upper gap-fill pattern on the lower gap-fill pattern;
a channel layer including a lower channel layer on a sidewall of the lower gap-fill pattern, an upper channel layer on a sidewall of the upper gap-fill pattern, and an intermediate channel layer between the lower gap-fill pattern and the upper gap-fill pattern, and

wherein the lower gap-fill pattern and the upper gap-fill pattern are spaced apart from each other by the intermediate channel layer.

2. The device of claim 1 ,
wherein a width of the lower portion is greater than a width of the upper portion,
wherein the upper gap-fill pattern includes:
a first gap-fill portion; and
a second gap-fill portion on the first gap-fill portion,

wherein a width of the first gap-fill portion is greater than a width of the second gap-fill portion, and
wherein the upper channel layer includes:
a first channel layer on a sidewall of the first gap-fill portion; and
a second channel layer extending from the first channel layer and on a sidewall of the second gap-fill portion.

3. The device of claim 2 ,
wherein the lower portion of the vertical channel structure includes:
the lower gap-fill pattern;
the first gap-fill portion;
the lower channel layer;
the intermediate channel layer; and
the first channel layer, and

wherein the upper portion of the vertical channel structure includes:
the second gap-fill portion; and
the second channel layer.

4. The device of claim 3 ,
wherein the lower portion of the vertical channel structure further includes a memory layer between the channel layer and the cell stack,
wherein the upper portion of the vertical channel structure further includes an insulating layer between the channel layer and the upper gate electrode,
wherein the memory layer is at a lower level than the upper gate electrode, and
wherein the insulating layer is at a higher level than an uppermost word line among the word lines.

5. The device of claim 4 , wherein the insulating layer is spaced apart from the memory layer.

6. The device of claim 1 , wherein the intermediate channel layer is at a lower level than an upper surface of an uppermost word line among the word lines.

7. The device of claim 1 , further comprising a pad pattern on the vertical channel structure,
wherein the pad pattern is between the plug and the vertical channel structure, and
wherein the pad pattern includes:
a polysilicon layer extending from the channel layer and on the upper gap-fill pattern; and
a metal silicide layer on the polysilicon layer.

8. The device of claim 1 ,
wherein the upper gate electrode includes a first material layer and a second layer-material layer on an upper surface of the first material layer,
wherein the first material layer includes polysilicon, and
wherein the second material layer includes metal silicide.

9. The device of claim 1 , further comprising a logic circuit overlapping the cell stack in the vertical direction,
wherein the channel layer contacts the source structure.

10. The device of claim 1 , wherein a thickness of the upper gate electrode is greater than a thickness of each of the plurality of word lines.

11. A three-dimensional memory device, comprising:
a source structure;
a cell stack on the source structure, the cell stack including a plurality of mold layers and a plurality of word lines alternately stacked in a vertical direction;
an upper gate electrode on the cell stack;
a string selection line separation pattern on a sidewall of the upper gate electrode;
a vertical channel structure including a lower portion and an upper portion on the lower portion;
a bit line on the vertical channel structure; and
a plug between the bit line and the vertical channel structure,
wherein the lower portion penetrates through the cell stack,
wherein the upper portion penetrates through the upper gate electrode,
wherein the upper gate electrode includes a first electrode portion and a second electrode portion extending from a portion of the first electrode portion in the vertical direction,
wherein the second electrode portion is adjacent to the vertical channel structure, and
wherein a first upper surface of the first electrode portion is at a lower level than a second upper surface of the second electrode portion.

12. The device of claim 11 ,
wherein a width of the lower portion is greater than a width of the upper portion,
wherein the upper gate electrode includes a first material layer and a second material layer on and contacting an upper surface of the first material layer,
wherein the first and second upper surfaces are an upper surface of the second material layer,
wherein the first and second upper surfaces are at a higher level than the upper surface of the first material layer, and
wherein a distance between the upper surface of the first material layer and a lower surface of the first material layer is greater than a distance between the first upper surface of the second material layer and a lower surface of the second material layer.

13. The device of claim 12 ,
wherein a thickness of the upper gate electrode is greater than a thickness of each of the plurality of word lines,
wherein the first material layer includes polysilicon, and
wherein the second material layer includes metal silicide.

14. The device of claim 12 , wherein the upper surface of the first material layer is substantially flat, and
wherein a sidewall of the first material layer contacts the string selection line separation pattern.

15. The device of claim 11 ,
wherein a width of the lower portion is greater than a width of the upper portion,
wherein the vertical channel structure includes:
a lower gap-fill pattern;
an upper gap-fill pattern on the lower gap-fill pattern;
a channel layer including a lower channel layer on a sidewall of the lower gap-fill pattern, an upper channel layer on a sidewall of the upper gap-fill pattern, and an intermediate channel layer between the lower gap-fill pattern and the upper gap-fill pattern,

wherein the lower gap-fill pattern and the upper gap-fill pattern are spaced apart from each other by the intermediate channel layer, and
wherein the intermediate channel layer is at a lower level than the upper gate electrode.

16. A three-dimensional memory device comprising:
a source structure;
a cell stack on the source structure, the cell stack including a plurality of mold layers and a plurality of word lines alternately stacked in a vertical direction;
upper gate electrodes on the cell stack, the upper gate electrodes including a first upper gate electrode and a second upper electrode adjacent to the first upper gate electrode in a horizontal direction perpendicular to the vertical direction;
string selection line separation

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kanamori Kohji
• Kang Seogoo
• Ahn Jongseon
• Han Jeehoon

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title