Photonic assembly for enhanced bonding yield and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12554064-B2
Application number	US-202318501064-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Nov 3, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

First claim

What is claimed is:

1 . A photonic assembly comprising:
an electronic integrated circuits (EIC) die comprising a semiconductor substrate, semiconductor devices located on a surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer having first metal bonding pads formed therein, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die comprising waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer having second metal bonding pads formed therein, wherein the second metal bonding pads are bonded to the first metal bonding pads.

2 . The photonic assembly of claim 1 , wherein the second metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding in which the second metal bonding pads are in direct contact with the first metal bonding pads.

3 . The photonic assembly of claim 1 , wherein the EIC die further comprises a dielectric protection liner laterally surrounding the dielectric pillar structure and contacting each of the first dielectric material layers.

4 . The photonic assembly of claim 3 , wherein the EIC die further comprises a semiconductor lens which comprises a portion of the semiconductor substrate, has a convex semiconductor surface, and is located between the dielectric pillar structure and the semiconductor substrate.

5 . The photonic assembly of claim 4 , wherein the dielectric protection liner contacts the convex semiconductor surface of the semiconductor lens and a vertically-extending sidewall of the semiconductor substrate.

6 . The photonic assembly of claim 3 , wherein:
the EIC die comprises passivation-level dielectric layers located between the first dielectric material layers and the first bonding-level dielectric layer; and a first one of the passivation-level dielectric layers is located between the first dielectric material layers and a horizontally-extending portion of the dielectric protection liner.

7 . The photonic assembly of claim 6 , wherein the first bonding-level dielectric layer is in contact with the horizontally-extending portion of the dielectric protection liner.

8 . The photonic assembly of claim 6 , wherein:
the first subset of the first metal bonding pads is not in direct contact with the horizontally-extending portion of the dielectric protection liner; and a second subset of the first metal bonding pads that does not have any areal overlap with the dielectric pillar structure in the plan view is in contact with the horizontally-extending portion of the dielectric protection liner.

9 . The photonic assembly of claim 6 , wherein:
a second one of the passivation-level dielectric layers comprises an etch-stop dielectric layer that is located between the horizontally-extending portion of the dielectric protection liner and the first bonding-level dielectric layer; and each first metal bonding pad selected from the first metal bonding pads comprises a respective bottom surface contacting a top surface of the etch-stop dielectric layer.

10 . The photonic assembly of claim 9 , wherein the first bonding-level dielectric layer is in contact with the etch-stop dielectric layer, and is vertically spaced from the dielectric protection liner.

11 . A photonic assembly comprising:
an electronic integrated circuits (EIC) die comprising a semiconductor substrate, a semiconductor lens which comprises a portion of the semiconductor substrate and has a convex semiconductor surface; semiconductor devices located on a surface of the semiconductor substrate, first dielectric material layers having first metal interconnect structures formed therein, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers and having an areal overlap with the semiconductor lens in a plan view; and a first bonding-level dielectric layer having first metal bonding pads formed therein, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in the plan view; and a photonic integrated circuits (PIC) die comprising waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer having second metal bonding pads formed therein, wherein the second metal bonding pads are bonded to the first metal bonding pads.

12 . The photonic assembly of claim 11 , wherein:
the EIC die comprises a dielectric protection liner laterally surrounding the dielectric pillar structure and contacting each of the first dielectric material layers; the EIC die comprises passivation-level dielectric layers located between the first dielectric material layers and the first bonding-level dielectric layer; and a first one of the passivation-level dielectric layers is located between the first dielectric material layers and a horizontally-extending portion of the dielectric protection liner.

13 . The photonic assembly of claim 12 , wherein an entirely of the first subset of the first metal bonding pads is located within an area defined by an inner sidewall of a vertically-extending portion of the dielectric protection liner that vertically extends through the first dielectric material layers in the plan view.

14 . The photonic assembly of claim 12 , wherein:
each first metal bonding pad within the first subset of the first metal bonding pads has a first thickness that is greater than a thickness of the first bonding-level dielectric layer and comprises a respective portion that protrudes into the dielectric pillar structure; and each first metal bonding pad within a second subset of the first metal bonding pads that does not have any areal overlap with the dielectric pillar structure in the plan view comprises a pad portion having a second thickness that is less than the first thickness and a via portion that extends through the dielectric protection liner.

15 . The photonic assembly of claim 12 , wherein at least one of the first subset of the first metal bonding pads has an areal overlap with a vertically-extending portion of the dielectric protection liner that vertically extends through the first dielectric material layers in the plan view.

16 . A method of forming a device structure, the method comprising:
forming semiconductor devices on a horizontal surface of a semiconductor substrate; forming first metal interconnect structures within first dielectric material layers over the semiconductor devices; forming a via cavity through the first dielectric material layers such that a portion of the semiconductor substrate is exposed underneath the via cavity; forming a semiconductor lens by patterning the portion of the semiconductor substrate underneath the via cavity; forming a dielectric pillar structure by filling the via cavity with a dielectric fill material; forming a first bonding-level dielectric layer over the first dielectric material layers and the dielectric pillar structure; and forming first metal bonding pads in the first bonding-level dielectric layer, whereby an electronic integrated circuits (EIC) die is formed, and wherein a first subset of the first metal bonding pads is formed with an areal overlap with t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yu-Hung
• Yu Chih-Hao
• Wang Wei-Ming
• Chen Chen
• Lin Chia-Hui
• Tsui Ren-Fen
• Yu Chen-Hua

Classifications

• H10W72/019

  of bond pads · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title