Oxide film coating solution and semiconductor device manufacturing method using the same

Patent metadata

Field	Value
Publication number	US-12543337-B2
Application number	US-202217693532-A
Country	US
Kind code	B2
Filing date	Mar 14, 2022
Priority date	Mar 31, 2021
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor device, the method comprising:
forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film, wherein forming the passivation film includes applying a coating solution on the field insulating film to form a coating layer, and heat-treating the coating layer to adsorb the coating layer to the upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

2 . The method for manufacturing the semiconductor device as claimed in claim 1 , wherein the coating solution includes:
a silane compound, and an organic solvent in which the silane compound is dissolved.

3 . The method for manufacturing the semiconductor device as claimed in claim 2 , wherein the silane compound is represented by Chemical Formula 1 or Chemical Formula 2 below:
(R) n —Si—(R′) m   (Chemical Formula 1)

in Chemical Formula 1,
R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group,
R′ is an alkyl, methoxy, ethoxy, chloro, or disilazane group,
n and m are integers of 1 to 3, and
n+m is 4,
(R 3 —Si) n —N—(H) m   (Chemical Formula 2)

in Chemical Formula 2,
R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group,
n and m are integers of 0 to 3, and
n+m is 3.

4 . The method for manufacturing the semiconductor device as claimed in claim 2 , wherein the silane compound is included in the coating solution in an amount of 5 wt % to 8 wt %, based on 100 wt % of the coating solution.

5 . The method for manufacturing the semiconductor device as claimed in claim 2 , wherein the organic solvent includes a ketone, a hydrocarbon, or an ether.

6 . The method for manufacturing the semiconductor device as claimed in claim 1 , further comprising:
removing the passivation film after removing the plurality of sacrificial layers; and forming a gate electrode that intersects the lower pattern after removing the passivation film.

7 . A method for manufacturing a semiconductor device, the method comprising:
forming a first fin type pattern including a first lower pattern and a first upper pattern on a first region of a substrate such that the first upper pattern includes a plurality of first sacrificial layers and a plurality of first sheet patterns alternately stacked on the first lower pattern; forming a second fin type pattern including a second lower pattern and a second upper pattern on a second region of the substrate such that the second upper pattern includes a plurality of second sacrificial layers and a plurality of second sheet patterns alternately stacked on the second lower pattern; forming a first field insulating film on the first region of the substrate such that the first field insulating film covers side walls of the first lower pattern; forming a second field insulating film on the second region of the substrate such that the second field insulating film covers side walls of the second lower pattern; forming an insulating liner on the second field insulating film, along profiles of an upper surface of the second field insulating film, and on the second upper pattern; forming a first passivation film on the first field insulating film, wherein forming the first passivation film includes applying a coating solution on the first field insulating film to form a first coating layer, and heat-treating the first coating layer to adsorb the first coating layer to an upper surface of the first field insulating film; forming a second passivation film on the insulating liner; and removing the plurality of first sacrificial layers, after forming the first passivation film and the second passivation film.

8 . The method for manufacturing the semiconductor device as claimed in claim 7 , wherein:
forming the second passivation film includes
applying the coating solution onto the insulating liner of the second region to form a second coating layer, and
heat-treating the second coating layer to adsorb the second coating layer to the insulating liner.

9 . The method for manufacturing the semiconductor device as claimed in claim 7 , wherein the coating solution includes:
a silane compound, and an organic solvent in which the silane compound is dissolved.

10 . The method for manufacturing the semiconductor device as claimed in claim 9 , wherein the silane compound is represented by Chemical Formula 1 or Chemical Formula 2 below:
(R) n —Si—(R) m   (Chemical Formula 1)
in Chemical Formula 1, R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group, R′ is an alkyl, methoxy, ethoxy, chloro, or disilazane group, n and m are integers of 1 to 3, and n+m is 4,
(R 3 —Si) n —N—(H) m   (Chemical Formula 2)

in Chemical Formula 2, R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group, n and m are integers of 0 to 3, and n+m is 3.

11 . The method for manufacturing the semiconductor device as claimed in claim 9 , wherein the silane compound is included in the coating solution in an amount of 5 wt % to 8 wt %, based on 100 wt % of the coating solution.

12 . The method for manufacturing the semiconductor device as claimed in claim 9 , wherein the organic solvent includes a ketone, a hydrocarbon, or an ether.

13 . The method for manufacturing the semiconductor device as claimed in claim 7 , wherein removing the plurality of first sacrificial layers includes:
forming a mask layer on the substrate of the second region, and processing an etching solution on the substrate of the first region exposed by the mask layer.

14 . The method for manufacturing the semiconductor device as claimed in claim 13 , wherein the etching solution includes hydrogen fluoride (HF) and percetic acid.

15 . The method for manufacturing the semiconductor device as claimed in claim 7 , wherein the first field insulating film and the second field insulating film each include SiO 2 .

16 . The method for manufacturing the semiconductor device as claimed in claim 7 , wherein the first passivation film is in contact with an upper surface of the first field insulating film and is not in contact with side surfaces of the plurality of first sacrificial layers.

17 . The method of claim 1 , wherein the passivation film is not formed on an uppermost surface of the upper pattern.

18 . The method of claim 7 , wherein the first passivation film is not formed on an uppermost surface of the first upper pattern.

Assignees

• Samsung Electronics Co Ltd
• Soulbrain Co Ltd

Inventors

• Yeom Chang Ju
• Jeon Chang Su
• Oh Jung Min
• Bae Sang Won
• Lee Jae Sung
• Lee Hyo San
• Lim Jung Hun

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H01L23/3171

  Electricity · mapped topic

• H01L23/291

  Electricity · mapped topic