Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2017345945-A1
Application number	US-201615373065-A
Country	US
Kind code	A1
Filing date	Dec 8, 2016
Priority date	May 30, 2016
Publication date	Nov 30, 2017
Grant date	—

Abstract

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

First claim

1 . A transistor, comprising:
a drain; a source; a gate electrode; and a first nanowire between the source and drain, wherein the first nanowire has a first section with a first thickness and a second section with a second thickness different from the first thickness, and wherein the second section is between the first section and at least one of the source or drain, the first nanowire to include a channel when a voltage is applied to the gate electrode.

2 . The transistor as claimed in claim 1 , wherein:
the first section overlaps the gate electrode, and the second section does not overlap the gate electrode.

3 . The transistor as claimed in claim 1 , further comprising:
at least one gate spacer, wherein the second section overlaps the at least one gate spacer.

4 . The transistor as claimed in claim 3 , wherein the second section is in a hole of the at least one spacer.

5 . The transistor as claimed in claim 1 , wherein:
the first section has a first surface, the second section has a second surface, and the first and second surfaces are in different planes.

6 . The transistor as claimed in claim 1 , wherein the first and second sections of the first nanowire are arranged to have substantially a barbell shape.

7 . The transistor as claimed in claim 1 , wherein the first nanowire has a third section between the first and second sections, and wherein the third section is inclined relative to the first and second sections.

8 . The transistor as claimed in claim 1 , wherein:
the first nanowire includes at least one dimple, and the at least one dimple is between a surface of the first section and a surface of the second section.

9 . The transistor as claimed in claim 1 , wherein the second section has rounded surfaces.

10 . The transistor as claimed in claim 1 , further comprising a fin-shaped pattern overlapping at least one of the source, the drain, or the first nanowire.

11 . The transistor as claimed in claim 1 , further comprising:
a second nanowire between the source and drain and overlapping the first nanowire.

12 . The transistor as claimed in claim 11 , wherein the second nanowire has a different shape from the first nanowire.

13 . The transistor as claimed in claim 11 , wherein the first and second nanowires have different cross-sectional areas.

14 . The transistor as claimed in claim 1 , wherein the second thickness is greater than the first thickness.

15 - 25 . (canceled)

26 . A semiconductor device, comprising:
a first region including a first transistor, the first transistor including a first gate electrode, a first source, a first drain, and a first nanowire between the first source and the first drain, the first nanowire having a first shape; and a second region including a second transistor, the second transistor including a second gate electrode, a second source, a second drain, and a second nanowire between the second source and the second drain, the second nanowire having a second shape different from the first shape.

27 . The semiconductor device as claimed in claim 26 , wherein the first and second nanowires include different materials.

28 . The semiconductor device as claimed in claim 26 , wherein:
the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

29 . The semiconductor device as claimed in claim 26 , wherein:
the first transistor includes a silicon (Si) channel region, and the second transistor includes an silicon germanium (SiGe) channel region.

30 - 36 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seung Hun
• Kim Dong Woo
• Suh Dong Chan
• Kim Sun Jung

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• Y10S977/938

  Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title

• Y10S977/762

  Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title