Quasi-monolithic die architectures

Patent metadata

Field	Value
Publication number	US-12538841-B2
Application number	US-202217821001-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a first die in a first layer, the first layer having a first surface and an opposing second surface, the first die surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a greater width towards the first surface of the first layer and a smaller width towards the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposing second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by interconnects having a pitch of less than 10 microns between adjacent interconnects, and wherein the second die is surrounded by the dielectric material and includes an interface seam extending from the second die at the second surface of the second layer towards the first surface of the second layer and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; and a substrate coupled to the second surface of the second layer.

2 . The microelectronic assembly of claim 1 , wherein the dielectric material includes silicon and one or more of nitrogen, oxygen, and carbon; a polyimide material; or a low-k or ultra low-k dielectric.

3 . The microelectronic assembly of claim 1 , wherein the dielectric material in the first layer is a first dielectric material and the dielectric in the second layer is a second dielectric material different than the first dielectric material.

4 . The microelectronic assembly of claim 1 , wherein the angle of the interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

5 . The microelectronic assembly of claim 1 , wherein the interface seam is a first interface seam, and wherein the dielectric material in the second layer further includes a second interface seam extending from the second die at the second surface of the second layer towards the first surface of the second layer and the second interface seam has an angle of less than 90 degrees relative to the second surface of the second layer.

6 . The microelectronic assembly of claim 5 , wherein the angle of the second interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

7 . The microelectronic assembly of claim 1 , wherein the TDV is electrically coupled to the second die.

8 . The microelectronic assembly of claim 1 , further comprising:
a package substrate electrically coupled to the first surface of the first layer by solder interconnects.

9 . The microelectronic assembly of claim 8 , wherein the TDV is electrically coupled to the package substrate at a first end and electrically coupled to the second die at an opposing second end.

10 . The microelectronic assembly of claim 1 , wherein a material of the substrate includes silicon.

11 . A microelectronic assembly, comprising:
a first layer having a first surface and an opposing second surface, the first layer including a first die, a dielectric material around the first die, and a through-dielectric via (TDV), wherein the TDV has a greater width towards the first surface of the first layer and a smaller width towards the second surface of the first layer; and a second layer having a first surface and an opposing second surface, the first surface of the second layer at the second surface of the first layer, the second layer including a second die, a third die, and the dielectric material on and between the second and third dies, wherein the first die is electrically coupled to the second and third dies by interconnects having a pitch of less than 10 microns between adjacent interconnects, wherein the TDV is electrically coupled to the second die, and wherein the dielectric material between the second and third dies includes an interface seam extending from the second die at the second surface of the second layer towards the third die at the first surface of the second layer and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer.

12 . The microelectronic assembly of claim 11 , wherein the angle of the interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

13 . The microelectronic assembly of claim 11 , wherein the interface seam is a first interface seam, and wherein the dielectric material between the second and third dies further includes a second interface seam extending from the third die at the second surface of the second layer towards the second die at the first surface of the second layer and the second interface seam has an angle of less than 90 degrees relative to the second surface of the second layer.

14 . The microelectronic assembly of claim 13 , wherein the angle of the second interface seam is between 35 degrees and 55 degrees relative to the second surface of the second layer.

15 . The microelectronic assembly of claim 11 , further comprising:
a substrate coupled to the second surface of the second layer by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

16 . The microelectronic assembly of claim 15 , wherein the substrate further includes conductive pathways and the conductive pathways are electrically coupled to the second die by the second interconnects.

17 . A microelectronic assembly, comprising:
a first die in a first layer, the first layer having a first surface and an opposing second surface, the first die surrounded by a dielectric material; a through-dielectric via (TDV) in the first layer, wherein the TDV has a greater width towards the first surface of the first layer and a smaller width towards the second surface of the first layer; a second die in a second layer, the second layer having a first surface and an opposing second surface, wherein the first surface of the second layer is at the second surface of the first layer, wherein the first die is electrically coupled to the second die by first interconnects having a pitch of less than 10 microns between adjacent first interconnects, and wherein the second die is surrounded by the dielectric material and includes an interface seam extending from the second die at the second surface of the second layer towards the first surface of the second layer and the interface seam has an angle of less than 90 degrees relative to the second surface of the second layer; a substrate coupled to the second surface of the second layer; and a package substrate electrically coupled to the first surface of the first layer by second interconnects.

18 . The microelectronic assembly of claim 17 , wherein a material of the substrate includes silicon.

19 . The microelectronic assembly of claim 17 , wherein the substrate is coupled to the second die by second interconnects having a pitch of less than 10 microns between adjacent second interconnects.

20 . The microelectronic assembly of claim 19 , wherein the substrate further includes conductive pathways and the conductive pathways are electrically coupled to the second die by the second interconnects.

Assignees

• Intel Corp

Inventors

• Yao Jimin
• Elsherbini Adel A
• Brun Xavier Francois
• Jun Kimin
• Liff Shawna M
• Swan Johanna M
• Shi Yi
• Talukdar Tushar
• Eid Feras
• Kabir Mohammad Enamul
• Karhade Omkar G
• Krishnatreya Bhaskar Jyoti

Classifications

• H01L2225/06548

  Electricity · mapped topic

• H01L2224/16227

  Electricity · mapped topic

• H01L2224/13155

  Electricity · mapped topic

• H01L2224/13147

  Electricity · mapped topic

• H01L2224/13139

  Electricity · mapped topic