Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

Patent metadata

Field	Value
Publication number	US-10872872-B2
Application number	US-201616347188-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

First claim

The invention claimed is:

1. An integrated circuit package, comprising:
a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers;
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via; and

a first die, wherein the first die is electrically coupled to the package substrate via the pillar on the high-density interconnect layer.

2. The integrated circuit package of claim 1 , wherein the first die is electrically coupled to the pillar.

3. The integrated circuit package of claim 1 , wherein the package substrate is electrically coupled to the via.

4. The integrated circuit package of claim 1 , further comprising:
a cavity formed on the package substrate.

5. The integrated circuit package of claim 4 , further comprising:
a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate.

6. The integrated circuit package of claim 5 , further comprising:
a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die.

7. The integrated circuit package of claim 1 , wherein an input/output (I/O) of an individual layer of the plurality of layers of the package substrate, that is not the high-density interconnect layer, is between 15 and 60 I/O/mm/layer.

8. A computing device, comprising:
a circuit board; and
an integrated circuit package coupled to the circuit board, wherein the integrated circuit package comprises:
a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers;
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via;
a first die, wherein the first die is electrically coupled to the package substrate via one or more of the plurality of pillars on the high-density interconnect layer.

9. The computing device of claim 8 , wherein the first die is electrically coupled to the one or more of the plurality of pillars.

10. The computing device of claim 8 , wherein the package substrate is electrically coupled to the via.

11. The computing device of claim 8 , further comprising:
a cavity formed on the package substrate.

12. The computing device of claim 11 , further comprising:
a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate.

13. The computing device of claim 12 , further comprising:
a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die.

14. An integrated circuit assembly, comprising:
a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers; and
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via.

15. The integrated circuit assembly of claim 14 , wherein an I/O of the next individual layer of the plurality of layers of the package substrate is between 15 and 60 I/O/mm/layer.

16. The integrated circuit assembly of claim 14 , wherein the first face of the package substrate is an active side and the second face of the package substrate is a back side, and wherein the back side has a bump pitch between 200 um and 1000 um.

17. The integrated circuit assembly of claim 14 , wherein the high-density interconnect layer further includes a pad formed on the second side of the high-density interconnect layer and the pad has a pad size between 1 um and 24 um.

Assignees

• Intel Corp

Inventors

• May Robert Alan
• Boyapati Sri Ranga Sai
• Darmawikarta Kristof Kuwawi
• Pietambaram Srinivas V
• Soto Gonzalez Javier
• Lim Kwangmo Chris
• Aleksov Aleksandar

Classifications

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title