Bumpless wafer level fan-out package

Patent metadata

Field	Value
Publication number	US-9806061-B2
Application number	US-201615087907-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further include a package substrate having a cavity, in which the interposer substrate and the integrated circuit are disposed in the cavity. The interposer substrate may include interconnect pathways that are electrically coupled to the first and second conductive pads. A heat spreader may subsequently form over the integrated circuit die and the package substrate.

First claim

What is claimed is:

1. An integrated circuit package comprising:
an interposer substrate;
a first conductive pad on the interposer substrate;
a second conductive pad formed on a front surface of an integrated circuit die, wherein the second conductive pad directly contacts the first conductive pad on the interposer substrate; and
a continuous package substrate having a cavity defined by a continuous wall comprising substantially the same material, wherein the interposer substrate and the integrated circuit die are disposed in the cavity.

2. The integrated circuit package defined in claim 1 , wherein each of the first and second conductive pads comprises a copper pad.

3. The integrated circuit package defined in claim 1 , comprising:
interconnect pathways that are formed in the interposer substrate and that are electrically coupled to the first and second conductive pads.

4. The integrated circuit package defined in claim 3 , wherein the interconnect pathways comprise copper traces.

5. The integrated circuit package defined in claim 1 , wherein the front surface of the integrated circuit die serves as an active surface of the integrated circuit die in which transistors are formed.

6. The integrated circuit package defined in claim 1 , wherein the package substrate comprises an organic substrate.

7. The integrated circuit package defined in claim 1 , comprising:
a heat spreader formed over the integrated circuit die and the package substrate.

8. The integrated circuit package defined in claim 7 , wherein the heat spreader comprises a flat heat spreader.

9. An integrated circuit package, comprising:
an interposer substrate having a surface, the interposer substrate having a plurality of conductive pads on the surface;
an integrated circuit die having front and back surfaces, wherein the integrated circuit die is mounted on the interposer substrate, and wherein the front surface of the integrated circuit die faces the interposer substrate;
a plurality of contact pads formed on the front surface of the integrated circuit die, each of which makes direct physical contact with a corresponding conductive pad in the plurality of conductive pads; and
a continuous package substrate having a continuous wall comprising substantially the same material that surrounds the interposer substrate and the integrated circuit die.

10. The integrated circuit package defined in claim 9 , comprising:
a plurality of interconnect pathways in the interposer substrate, each of which is coupled to a corresponding conductive pad of the plurality of conductive pads.

11. The integrated circuit package defined in claim 10 , comprising:
an additional integrated circuit die that is mounted on the interposer substrate and that is coupled to the integrated circuit die through the plurality of interconnect pathways of the interposer substrate.

12. The integrated circuit package defined in claim 10 , wherein the plurality of interconnect pathways is disposed in a fan-out arrangement.

13. The integrated circuit package defined in claim 9 , wherein the package substrate has top and bottom surfaces, and wherein the integrated circuit package comprises:
a heat spreader disposed over the back surface of the integrated circuit die on the top surface of the package substrate.

14. The integrated circuit package defined in claim 13 , comprising:
a molding compound formed between the interposer substrate and the heat spreader and surrounding the integrated circuit die.

15. The integrated circuit package defined in claim 9 , wherein the package substrate has top and bottom surfaces, and wherein the integrated circuit package comprises:
a molding compound formed between the interposer substrate and the heat spreader and surrounding the integrated circuit die.

16. A method of fabricating an integrated circuit package, comprising:
forming a first plurality of conductive pads on an interposer substrate;
forming a second plurality of conductive pads on an integrated circuit die;
assembling the integrated circuit die on the interposer substrate so that each conductive pad in the second plurality of conductive pads makes direct physical contact with a corresponding conductive pad in the first plurality of conductive pads; and
embedding the integrated circuit die and the interposer substrate in a continuous package substrate to form the integrated circuit package, wherein the integrated circuit die and the interposer are surrounded by a continuous wall of the continuous package substrate, comprising substantially the same material.

17. The method defined in claim 16 , comprising:
forming a plurality of interconnect pathways in the interposer substrate, each of which is coupled to a corresponding conductive pad of the second plurality of conductive pads.

18. The method defined in claim 17 , comprising:
assembling an additional integrated circuit die on the interposer substrate, wherein the additional integrated circuit is coupled to the integrated circuit die through the plurality of interconnect pathways.

19. The method defined in claim 16 , comprising:
forming a heat spreader on the integrated circuit package.

20. The method defined in claim 19 , comprising:
depositing a molding compound between the interposer substrate and the heat spreader and surrounding the integrated circuit die.

Assignees

• Altera Corp

Inventors

• Shen Minghao

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/016

  using moulds · CPC title

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title