Wafer-level fan-out wirebond packages

Patent metadata

Field	Value
Publication number	US-9842820-B1
Application number	US-201514960180-A
Country	US
Kind code	B1
Filing date	Dec 4, 2015
Priority date	Dec 4, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An integrated circuit package that includes an integrated circuit die, a redistribution substrate, a wirebond interconnect and a package substrate is disclosed. The redistribution substrate is formed on the integrated circuit die and may be wider than the integrated circuit die. The package substrate is formed below the integrated circuit die. The wirebond interconnect may have one of its ends attached to the redistribution substrate and another end attached to the package substrate. In addition to that, another integrated circuit die may be formed between the redistribution substrate and the package substrate. The integrated circuit dies may communicate with each other through the redistribution substrate. In addition to that, a method to manufacture the integrated circuit package may also be disclosed.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
a package substrate having a top surface;
a first integrated circuit die that is mounted on the top surface of the package substrate;
a second integrated circuit die that is mounted on the top surface of the package substrate, wherein the first and second integrated circuit dies are laterally adjacent;
a redistribution layer that is formed on a surface of the first integrated circuit die and a surface of the second integrated circuit die, wherein the redistribution layer is wider than the first integrated circuit die and the second integrated circuit die;
a wirebond interconnect having an end that is coupled to the redistribution layer;
a first wirebond pad that is formed on the redistribution layer and that is coupled to the wirebond interconnect; and
a second wirebond pad that is formed on the top surface of the package substrate, wherein the second wirebond pad and the first and second integrated circuit dies are mounted on the same plane at the top surface of the package substrate, and wherein the wirebond interconnect has another end that is coupled to the second wirebond pad.

2. The integrated circuit package as defined in claim 1 , wherein the redistribution layer conveys signals between the first integrated circuit die and the first wirebond pad.

3. The integrated circuit package as defined in claim 2 , wherein the package substrate is selected from a group of package types consisting of: grid array packages and lead frame packages.

4. The integrated circuit package as defined in claim 1 , wherein the redistribution layer includes multiple layers of conductive routing traces and conductive vias formed in dielectric material.

5. The integrated circuit package as defined in claim 4 , wherein the dielectric material is formed from a material selected from a group of materials consisting of: polyimide, polybenzoxazoles, and benzocyclobuten.

6. An integrated circuit package, comprising:
first and second laterally adjacent integrated circuit dies;
a routing layer formed on the first integrated circuit die and on the second integrated circuit die, wherein the first integrated circuit die communicates with the second integrated circuit die through the routing layer, wherein the routing layer includes a first conductive routing trace, a second conductive routing trace, and a conductive via interposed between the first and second conductive routing traces, and wherein the first and second conductive routing traces are separated by dielectric material; and
a bonding wire having an end that is coupled to the routing layer.

7. The integrated circuit package as defined in claim 6 , further comprising:
a package substrate on which the first and second integrated circuit dies are mounted, wherein the bonding wire has another end that is coupled to the package substrate.

8. The integrated circuit package as defined in claim 7 , further comprising:
a plurality of bond pads formed on a top surface of the package substrate, wherein the first and second integrated circuit dies are mounted on a top surface of the package substrate, and wherein the bonding wire is coupled to one of the plurality of bond pads.

9. The integrated circuit package as defined in claim 8 , wherein the plurality of bond pads is selected from a group of bond pads consisting of: ball grid array (BGA) interconnects, a land grid array (LGA) interconnects, and quad flat no-leads (QFN) interconnects.

10. The integrated circuit package as defined in claim 6 , wherein the first and second integrated circuit dies are different.

11. The integrated circuit package as defined in claim 6 , wherein the package substrate is larger in size than the first and second integrated circuit dies and is larger than the routing layer.

12. The integrated circuit package as defined in claim 6 , wherein the routing layer conveys signals between the first and second integrated circuit dies.

13. A method of forming an integrated circuit package, comprising:
forming an integrated circuit die having a dielectric stack;
forming a routing layer on the integrated circuit die, wherein the routing layer includes alternating conductive routing layers and conductive via layers separated by dielectric material, and wherein the routing layer is separate from the dielectric stack;
forming a wirebond pad over the routing layer;
mounting the integrated circuit die on a package substrate; and
attaching one end of a wirebond interconnect to the wirebond pad.

14. The method as defined in claim 13 , further comprising:
attaching another end of the wirebond interconnect to the package substrate.

15. The method as defined in claim 14 , further comprising:
forming another integrated circuit die that is interposed between the routing layer and the package substrate, wherein the integrated circuit die and the another integrated circuit die are laterally adjacent and communicate via the routing layer.

16. The method as defined in claim 15 , further comprising:
attaching one end of another wirebond interconnect to another wirebond pad on the top surface of the routing layer.

17. The method as defined in claim 14 , wherein the integrated circuit package is a type of package selected from a group of packages consisting of: grid array packages and lead frame packages.

Assignees

• Altera Corp

Inventors

• Shen Minghao

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title