Scan driver

Patent metadata

Field	Value
Publication number	US-12531012-B2
Application number	US-202418642778-A
Country	US
Kind code	B2
Filing date	Apr 22, 2024
Priority date	Nov 30, 2018
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

First claim

What is claimed is:

1 . A display device comprising:
a pixel area comprising a pixel; and a scan driver comprising a plurality of scan stages, the scan driver being located outside of the pixel area, wherein the pixel comprises: a first pixel transistor between a first pixel power line and a second pixel power line; and a second pixel transistor coupling a gate electrode of the first pixel transistor to a first electrode of the first pixel transistor, and wherein a scan stage from among the plurality of scan stages comprises: a first transistor having a first electrode coupled to an output scan line coupled to a gate electrode of the second pixel transistor, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a first clock line; a fourth transistor coupling the first electrode of the second transistor to the gate electrode of the second transistor; a first capacitor coupling the first electrode of the second transistor to the gate electrode of the second transistor; and wherein the second pixel transistor is an n-type transistor, and wherein the first, second, third, and fourth transistors are p-type transistors.

2 . The display device of claim 1 , wherein the scan stage further comprises:
a fifth transistor having a first electrode, a second electrode, and a gate electrode, the second electrode and the gate electrode being coupled to a second input scan line; and a sixth transistor having a first electrode coupled to the second node, a second electrode coupled to the first electrode of the fifth transistor, and a gate electrode coupled to a control line, wherein the first input scan line and the second input scan line are different from each other.

3 . The display device of claim 2 , wherein the scan stage further comprises:
a second capacitor having a first electrode coupled to a third node and a second electrode coupled to the first node; and a seventh transistor having a first electrode coupled to the third node, a second electrode coupled to a second clock line, and a gate electrode coupled to the first node.

4 . The display device of claim 3 , wherein the scan stage further comprises an eighth transistor having a first electrode coupled to a second power line, a second electrode coupled to the third node, and a gate electrode coupled to a third clock line.

5 . The display device of claim 3 , wherein the scan stage further comprises an eighth transistor having a first electrode coupled to the second clock line, a second electrode coupled to the third node, and a gate electrode coupled to a third clock line.

6 . The display device of claim 4 , wherein the scan stage further comprises a ninth transistor having a first electrode coupled to the first node, a second electrode coupled to the first electrode of the third transistor, and a gate electrode coupled to the first power line.

7 . The display device of claim 6 , wherein the scan stage further comprises a tenth transistor having a first electrode coupled to the second power line, a second electrode coupled to the second electrode of the fourth transistor, and a gate electrode coupled to the second input scan line.

8 . The display device of claim 7 , wherein the scan stage further comprises an eleventh transistor having a first electrode coupled to the second electrode of the fourth transistor, a second electrode coupled to the first power line, and a gate electrode coupled to the second input scan line.

9 . The display device of claim 4 , wherein pulses of a first scan signal input to the first input scan line have a phase faster than that of pulses of a second scan signal input to the second input scan line.

10 . The display device of claim 9 ,
wherein a fourth clock line is coupled to the first electrode of the second transistor, wherein a first clock signal is input to the first clock line, wherein a second clock signal is input to the second clock line, wherein a third clock signal is input to the third clock line, and wherein the pulses of the second scan signal overlap with some pulses of a fourth clock signal input to the fourth clock line for a partial time.

11 . The display device of claim 10 , wherein times at which the pulses of the second scan signal are generated are prior to those at which the some pulses of the fourth clock signal are generated.

12 . The display device of claim 11 , wherein the first clock signal has a same period length as the second clock signal, but has a phase faster than that of the second clock signal.

13 . The display device of claim 12 , wherein the pulses of the fourth clock signal have a polarity opposite to that of pulses of the second clock signal,
wherein the pulses of the fourth clock signal and the pulses of the second clock signal overlap with each other for a partial time, and wherein the pulses of the fourth clock signal have a phase delayed from that of the pulses of the second clock signal.

14 . The display device of claim 13 ,
wherein pulses of the third clock signal have a polarity opposite to that of the pulses of the fourth clock signal, wherein the pulses of the third clock signal and the pulses of the fourth clock signal overlap with each other for a partial time, and wherein the pulses of the third clock signal have a phase delayed from that of the pulses of the fourth clock signal.

15 . The display device of claim 12 , wherein the pulses of the fourth clock signal have a polarity opposite to that of the pulses of the second clock signal,
wherein the pulses of the fourth clock signal are generated for times at which the pulses of the second clock signal are generated, and wherein times at which the pulses of the fourth clock signal are generated are delayed from those at which the pulses of the second clock signal are generated.

16 . The display device of claim 15 ,
wherein pulses of the third clock signal have a polarity opposite to that of the pulses of the fourth clock signal, and wherein the pulses of the third clock signal do not temporally overlap with the pulses of the fourth clock signal.

17 . The display device of claim 4 , wherein, in a first driving mode, a control signal applied to the control line maintains a turn-on level during one period including a plurality of image frames.

18 . The display device of claim 17 , wherein, in a second driving mode different from the first driving mode, the control signal maintains the turn-on level during a partial period of the one period, and maintains a turn-off level during another partial period of the one period.

19 . The display device of claim 17 , wherein, in a second driving mode different from the first driving mode, the control signal maintains the turn-on level during the one period, and
wherein a clock signal input to the first electrode of the second transistor includes pulses during a partial period of the one period, and does not include the pulses during another partial period of the one period.

20 . The display device of claim 10 , wherein the pulses of the first scan signal input to the first input scan line have a phase faster than that of the pulses of the second scan signal input to the second input scan l

Assignees

• Samsung Display Co Ltd

Inventors

• Kang Chul Kyu
• Kim Sung Hwan
• Oh Soo Hee
• Lee Dong Sun
• Choi Sang Moo

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title