Dual scan correction for power fluxuations

Patent metadata

Field	Value
Publication number	US-9275582-B2
Application number	US-201314047850-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	May 9, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A scan driver includes scan-driving blocks, each including a first transistor having a gate coupled to a first node to supply a first power to an output terminal, a second transistor having a gate coupled to a second node to couple a second clock to the output terminal, a third transistor having a gate coupled to a first input to supply the first power to the first node, a fourth transistor having a gate coupled to a second input to supply a second power to the first node, and a fifth transistor having a gate coupled to a first clock to couple the first input to the second node. A first scan-driving block further includes a sixth transistor coupled between the second input and the fourth transistor gate, and a NOT gate configured to invert the first input signal and to supply the inverted signal to the sixth transistor gate.

First claim

What is claimed is:

1. A scan driver comprising:
a plurality of scan-driving blocks, each of the scan-driving blocks comprising:
a first transistor having a gate electrode coupled to a first node and configured to supply a first power source voltage to an output terminal in response to a voltage of the first node;
a second transistor having a gate electrode coupled to a second node and configured to couple a second clock signal input terminal to the output terminal;
a third transistor having a gate electrode coupled to a first signal input terminal and configured to supply the first power source voltage to the first node in response to a first signal being applied to the first signal input terminal;
a fourth transistor having a gate electrode coupled to a second signal input terminal and configured to supply a second power source voltage directly to the first node; and
a fifth transistor having a gate electrode coupled to a first clock signal input terminal and configured to transmit the first signal from the first signal input terminal to the second node,

wherein a first scan-driving block of the scan-driving blocks further comprises:
a sixth transistor directly coupled between the second signal input terminal and the gate electrode of the fourth transistor and configured to transmit a second signal from the second signal input terminal directly to the gate electrode of the fourth transistor; and
a NOT gate separate from the first through sixth transistors, directly coupled to the first signal input terminal, and configured to invert the first signal input through the first signal input terminal and to supply the inverted first signal directly to the gate electrode of the sixth transistor.

2. The scan driver of claim 1 , wherein each of the scan-driving blocks further comprises a first capacitor including a first terminal coupled to the first power source voltage and a second terminal coupled to the first node.

3. The scan driver of claim 1 , wherein each of the scan-driving blocks further comprises a second capacitor including a first terminal coupled to the second node and a second terminal coupled to the output terminal.

4. The scan driver of claim 1 , wherein each of the scan-driving blocks further comprises a third capacitor including a first terminal coupled to the first power source voltage and a second terminal coupled to the output terminal.

5. The scan driver of claim 1 , wherein the first signal input terminal of the first scan-driving block is configured to receive a frame start signal as the first signal, and the first signal input terminal of each of the scan-driving blocks after the first scan-driving block is configured to receive a scan signal from a corresponding previous one of the scan-driving blocks as the first signal.

6. The scan driver of claim 1 , wherein the second signal input terminal of each of the scan-driving blocks before a final one of the scan-driving blocks is configured to receive a scan signal of a corresponding next one of the scan-driving blocks as the second signal.

7. A display device comprising:
a plurality of pixels;
a scan driver configured to sequentially apply scan signals of a gate-on voltage to a plurality of scan lines coupled to the pixels; and
a data driver configured to apply data signals to a plurality of data lines coupled to the pixels,
wherein the scan driver comprises a plurality of scan-driving blocks, and
wherein a first scan-driving block of the scan-driving blocks comprises:
a first transistor having a gate electrode coupled to a first node and configured to supply a first power source voltage to an output terminal in response to a voltage of the first node;
a second transistor having a gate electrode coupled to a second node and configured to couple a second clock signal input terminal to the output terminal;
a third transistor having a gate electrode coupled to a first signal input terminal and configured to supply the first power source voltage to the first node in response to a first signal being applied to the first signal input terminal;
a fourth transistor having a gate electrode coupled to a second signal input terminal and configured to supply a second power source voltage directly to the first node;
a fifth transistor having a gate electrode coupled to a first clock signal input terminal and configured to transmit the first signal from the first signal input terminal to the second node;
a sixth transistor directly coupled between the second signal input terminal and the gate electrode of the fourth transistor and configured to transmit a second signal from the second signal input terminal directly to the gate electrode of the fourth transistor; and
a NOT gate separate from the first through sixth transistors, directly coupled to the first signal input terminal, and configured to invert the first signal input through the first signal input terminal and to supply the inverted first signal directly to the gate electrode of the sixth transistor.

8. The display device of claim 7 , wherein the first scan-driving block further comprises a first capacitor including a first terminal coupled to the first power source voltage and a second terminal coupled to the first node.

9. The display device of claim 7 , wherein the first scan-driving block further comprises a second capacitor including a first terminal coupled to the second node and a second terminal coupled to the output terminal.

10. The display device of claim 7 , wherein the first scan-driving block further comprises a third capacitor including a first terminal coupled to the first power source voltage and a second terminal coupled to the output terminal.

11. The display device of claim 7 , wherein the first signal input terminal of the first scan-driving block is configured to receive a frame start signal as the first signal, and the second signal input terminal of the first scan-driving block is configured to receive a scan signal from a second one of the scan-driving blocks as the second signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Jin-Wook
• Gu Bon-Seog

Classifications

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title