GOA circuit, display substrate and display device

Patent metadata

Field	Value
Publication number	US-9324272-B2
Application number	US-201414476130-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	May 26, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A Gate Driver on Array (GOA) circuit according to this disclosure may include M cascaded GOA units. The M GOA units may have a one-to-one correspondence with M rows of pixels within a pixel region. And a Gate signal and a Reset signal may be outputted from each GOA unit. A Gate signal output from a GOA unit in an n-th row may be an input signal of a GOA unit in an (n+1)-th, where n is a natural number less than M.

First claim

What is claimed is:

1. A Gate Driver on Array (GOA) circuit comprising M cascaded GOA units, wherein:
the M cascaded GOA units have a one-to-one correspondence with M rows of pixels within a pixel region,
a first GOA unit of the M cascaded GOA units corresponds to an n-th row of the M rows of pixels,
n is a natural number less than M,
a second GOA unit of the M cascaded GOA units corresponds to an (n+1)-th row of the M rows of pixels,
each of the M cascaded GOA units outputs a Gate signal and a Reset signal,
the second GOA unit comprises: (i) a Reset signal output module configured to receive a Reset input signal and output the Reset signal and (ii) a Gate signal output module configured to receive a Gate input signal and output the Gate signal,
the Gate signal output from the first GOA unit is connected as the Reset input signal of the second GOA unit and the Gate input signal of the second GOA unit,
the Reset signal output module includes (i) a first clock signal input terminal CLK 1 , (ii) a second clock signal input terminal CLK 2 , (iii) a third clock signal input terminal CLK 3 , (iv) a signal input terminal, (v) a Reset signal output terminal, (vi) a first thin film transistor, (vii) a second thin film transistor, (viii) a third thin film transistor, (ix) a fourth thin film transistor, (x) a fifth thin film transistor, and (xi) a sixth thin film transistor,
a gate electrode of the first thin film transistor is connected to a drain electrode of the fifth thin film transistor, a source electrode of the first thin film transistor is connected to the CLK 2 , and a drain electrode of the first thin film transistor is connected to the Reset signal output terminal so as to output the Reset signal to outside, and a first capacitor is connected between the gate electrode and the drain electrode of the first thin film transistor,
a gate electrode of the second thin film transistor is connected to a high level via a second capacitor, the gate electrode of the second thin film transistor is connected to a drain electrode of the third thin film transistor, a source electrode of the second thin film transistor is connected to the high level, and a drain electrode of the second thin film transistor is connected to the Reset signal output terminal so as to output the Reset signal to outside,
a gate electrode of the third thin film transistor is connected to the CLK 3 , a source electrode of the third thin film transistor is connected to a low level, and a drain electrode of the third thin film transistor is connected to a drain electrode of the fourth thin film transistor,
a gate electrode of the fourth thin film transistor is connected to the signal input terminal, a source electrode of the fourth thin film transistor is connected to the high level, and the drain electrode of the fourth thin film transistor is connected to the drain electrode of the third thin film transistor,
a gate electrode of the fifth thin film transistor is connected to the CLK 1 , a source electrode of the fifth thin film transistor is connected to the signal input terminal, a drain electrode of the fifth thin film transistor is connected to the gate electrode of the first thin film transistor, and the drain electrode of the fifth thin film transistor is connected to a drain electrode of the sixth thin film transistor, and
a gate electrode of the sixth thin film transistor is connected to the high level via the second capacitor, the gate electrode of the sixth thin film transistor is connected to the drain electrode of the third thin film transistor, a source electrode of the sixth thin film transistor is connected to the high level, and the drain electrode of the sixth thin film transistor is connected to the drain electrode of the fifth thin film transistor.

2. The GOA circuit according to claim 1 , wherein:
the first GOA unit corresponds to a first row of the M rows of pixels, and
an input signal of the first GOA unit is a Start Vertical (STV) signal.

3. The GOA circuit according to claim 1 , wherein:
the Reset signal output from the first GOA unit is connected to an input terminal of a pixel Reset signal of a pixel in the n-th row, and
the Gate signal output from the second GOA unit is connected to an input terminal of a pixel Gate signal of the pixel in the n-th row.

4. The GOA circuit according to claim 1 , wherein:
the Gate signal output module of the second GOA unit comprises: (i) a first clock signal input terminal CLK 1 , (ii) a second clock signal input terminal CLK 2 , (iii) a third clock signal input terminal CLK 3 , (iv) a signal input terminal, (v) a Gate signal output terminal, (vi) a seventh thin film transistor, (vii) an eighth thin film transistor, (viii) a ninth thin film transistor, (ix) a tenth thin film transistor, (x) an eleventh thin film transistor, and (xi) a twelfth thin film transistor;
a gate electrode of the seventh thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the seventh thin film transistor is connected to the CLK 2 of the Gate signal output module, and a drain electrode of the seventh thin film transistor is connected to the Gate signal output terminal so as to output the Gate signal to outside;
a gate electrode of the eighth thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the eighth thin film transistor is connected to the Gate signal output terminal, and a drain electrode of the eighth thin film transistor is connected to the CLK 2 of the Gate signal output module;
a gate electrode of the ninth thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the ninth thin film transistor is connected to the Gate signal output terminal, and a drain electrode of the ninth thin film transistor is connected to the CLK 2 of the Gate signal output module;
a gate electrode of the tenth thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the tenth thin film transistor is connected to the Gate signal output terminal, and a drain electrode of the tenth thin film transistor is connected to the CLK 2 of the Gate signal output module;
a gate electrode of the eleventh thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the eleventh thin film transistor is connected to the Gate signal output terminal, and a drain electrode of the eleventh thin film transistor is connected to the CLK 2 of the Gate signal output module; and
a gate electrode of the twelfth thin film transistor is connected to the CLK 1 of the Gate signal output module, a source electrode of the twelfth thin film transistor is connected to the Gate signal output terminal, and a drain electrode of the twelfth thin film transistor is connected to the CLK 2 of the Gate signal output module.

5. A display substrate on which a Gate Driver on Array (GOA) circuit and M rows of pixels in a pixel region are integrated, wherein:
the GOA circuit comprises M cascaded GOA units,
the M cascaded GOA units have a one-to-one correspondence with M rows of pixels,
a first GOA unit of the M cascaded GOA units corresponds to an n-th row of the M rows of pixels,
n is a natural number less than M,
a second GOA unit of the M cascaded GOA units corresponds to an (n+1)-th row of the M rows of pixels,
each of the M cascaded GOA units outputs a Gate signal and a Reset signal,
the second GOA unit comprises: (i) a Reset signal output module configured to receive a Reset input signal and output the Reset signal and (ii) a Gate signal output module configured to receive a Gate input signal and output the Gate signal,
the Gate signal output from the first GOA unit is connected as the Reset input signal of the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Libin

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/062

  Waveforms for resetting a plurality of scan lines at a time · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3225

  using an active matrix · CPC title